Array substrate motherboard, display panel motherboard, and fabricating method thereof

A method for fabricating an array substrate motherboard, comprising:

• providing a substrate including a plurality of gate lines, gate line driving leads, data lines, and data line driving leads, wherein each gate line corresponds to one gate line driving lead, and each data line corresponds to one data line driving lead;
• forming a plurality of gate line testing leads, wherein each gate line testing lead is connected with a corresponding gate line driving lead;
• forming a plurality of data line testing leads, wherein each data line testing lead is connected with a corresponding subset of the plurality of data line driving leads;
• forming a plurality of gate line testing pads, wherein each gate line testing pad is connected with a corresponding gate line testing lead;
• forming a plurality of data line testing pads, wherein each data line testing pad is connected with two corresponding data line testing leads, wherein:
• a number of the data line testing pads is six,
• a first data line testing pad is interconnected with a subset of data line driving leads carrying a first red signal through two data line testing leads,
• a second data line testing pad is interconnected with a subset of data line driving leads carrying a first green signal through two data line testing leads,
• a third data line testing pad is interconnected with a subset of data line driving leads carrying a first blue signal through two data line testing leads,
• a fourth data line testing pad is interconnected with a subset of data line driving leads carrying a second red signal through two data line testing leads,
• a fifth data line testing pad is interconnected with a subset of data line driving leads carrying a second green signal through two data line testing leads, and
• a sixth data line testing pad is interconnected with a subset of data line driving leads carrying a second blue signal through two data line testing leads;
• and
• using the plurality of gate line testing pads and the plurality of gate line testing pads to test the plurality of gate lines and the plurality of data lines.