US 10,248,156 B2Granted

Data processing device

AssigneeRenesas Electronics Corporation

InventorsYoichi Yuyama, Kiwamu Takada

Life of this patent

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Abstract

In a data processing device including two sets of circuit pairs which are respectively duplicated in two clock domains which are asynchronous to each other, an asynchronous transfer circuit that transfers a payload signal is provided between the two sets of circuit pairs. The asynchronous transfer circuit includes two sets of a pair of bridge circuits which are respectively connected to the two sets of circuit pairs, and asynchronously transfers the payload signal and a control signal indicating a timing at which the payload signal is stable on a reception side. The two sets of a pair of bridge circuits and the payload signals can be duplicated, but the control signal is not duplicated, and the received payload signal is used for timing control to supply an expected same time difference, to the pair of duplicated circuits. This enables asynchronous transfer between circuits duplicated in the asynchronous clock domains.

Claims20

Dependent claims

A data processing device comprising:

a first body circuit and a first check circuit which are duplicated to each other in a first clock domain;
a second body circuit and a second check circuit which are duplicated to each other in a second clock domain which is asynchronous to the first clock domain;
and
an asynchronous transfer circuit that transfers a payload signal between the first clock domain and the second clock domain,
wherein the asynchronous transfer circuit
includes a first body-side bridge circuit and a first check-side bridge circuit which are respectively connected to the first body circuit and the first check circuit and are duplicated to each other in the first clock domain, and a second body-side bridge circuit and a second check-side bridge circuit which are respectively connected to the second body circuit and the second check circuit and are duplicated to each other in the second clock domain, and
has control signals which are generated by first or second body-side bridge circuit which transmits the payload signal and indicate a timing at which the payload signal is stable on a reception side, compares the control signal and check control signal which are generated by the corresponding first or second check-side bridge circuit, and in a case of mismatch, detects as a failure.

4 more elements

A data processing device comprising:

a first body circuit and a first check circuit which operate in synchronization with a first clock, and are duplicated to each other so as to respectively perform the same processing;
a second circuit which operates in synchronization with a second clock which is asynchronous to the first clock;
and
an asynchronous transfer circuit that performs asynchronous transfer of a payload signal, between the first body circuit and the first check circuit, and the second circuit,
wherein the asynchronous transfer circuit includes a first bridge circuit which operates in synchronization with the first clock and is connected to the first body circuit and the first check circuit, and a second bridge circuit which operates in synchronization with the second clock and is connected to the second circuit, and the first bridge circuit and the second bridge circuit are connected with each other through the payload signal and an asynchronous transfer control signal indicating a timing at which the payload signal is stable on the reception side,
wherein the first bridge circuit includes a first body-side conversion circuit that converts input and output signals to and from the first body circuit into a first body-side payload signal and first body-side asynchronous transfer control signals, a first check-side conversion circuit that converts input and output signals to and from the first check circuit into a first check-side payload signal and first check-side asynchronous transfer control signals, and a first comparison circuit that compares an output signal to be transmitted to the second bridge circuit among the first body-side asynchronous transfer control signals and the corresponding output signal among the first check-side asynchronous transfer control signals, and detects mismatch,
wherein the first bridge circuit transmits the output signal among the first body-side asynchronous transfer control signals as the output signal among the asynchronous transfer control signals, to the second bridge circuit, and
wherein the second bridge circuit receives the payload signal, at a timing indicated by the input signal, among the asynchronous transfer control signals which are received from the first bridge circuit, and provides the payload signal to the second circuit.

5 more elements

A data processing device comprising:

a first body circuit and a first check circuit which operate in synchronization with a first clock, and are duplicated to each other so as to respectively perform the same processing;
a second circuit which operates in synchronization with a second clock which is asynchronous to the first clock;
and
an asynchronous transfer circuit that performs asynchronous transfer of a payload signal between the first body circuit and the first check circuit, and the second circuit,
wherein the asynchronous transfer circuit includes a first bridge circuit which operates in synchronization with the first clock and is connected to the first body circuit and the first check circuit, and a second bridge circuit which operates in synchronization with the second clock and is connected to the second circuit, and the first bridge circuit and the second bridge circuit are connected with each other through the payload signal and an asynchronous transfer control signal indicating a timing at which the payload signal is stable on the reception side,
wherein the first bridge circuit includes a first body-side conversion circuit that converts input and output signals to and from the first body circuit into a first body-side payload signal and first body-side asynchronous transfer control signals, a first check-side conversion circuit that converts input and output signals to and from the first check circuit into a first check-side payload signal and first check-side asynchronous transfer control signals, and a second comparison circuit that compares an output signal to be transmitted to the second bridge circuit among the first body-side asynchronous transfer control signals and the corresponding output signal among the first check-side asynchronous transfer control signals, and detects mismatch, and
wherein the first bridge circuit receives the payload signal, at a timing indicated by the input signal, among the asynchronous transfer control signals which are transferred from the second bridge circuit, and provides the payload signal to the first body circuit through the first body-side conversion circuit, and to the first check circuit through the first check-side conversion circuit, respectively.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/502,771Filed 20 Mar 2015
Published: US 2017/0227981 A110 Aug 2017
Granted: 2 Apr 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 1/06
Generating or distributing clock signals or signals derived directly therefrom: clock generators producing several clock signals
G06F 11/1608
Error detection or correction of the data by redundancy in hardware: error detection by comparing the output signals of redundant hardware
G06F 11/1625
Error detection by comparing the output signals of redundant hardware: in communications, e.g. transmission, interfaces
G06F 11/1641
Error detection by comparing the output of redundant processing systems: where the comparison is not performed by the redundant processing components