Electronic memory devices
AssigneeLancaster University Business Enterprises Limited
InventorManus Hayne
Life of this patent
Estimating the term…
Abstract
A memory cell for storing one or more bits of information has a control gate, a source terminal and a drain terminal. A semiconductor substrate is located between the source and drain terminals, and a floating gate is disposed between the control gate and the semiconductor substrate. The floating gate is electrically isolated from the control gate by a charge trapping barrier, and is electrically isolated from the semiconductor substrate by a charge blocking barrier. At least one of the charge trapping barrier and the charge blocking barrier contains a III-V semiconductor material. The charge trapping barrier is adapted to enable the selective passage of charge carriers between the control gate and the floating gate, in use, to modify the one or more bits of information stored by the memory cell.
Claims24
A memory cell for storing one or more bits of information, the memory cell comprising a control gate, a source terminal and a drain terminal, a semiconductor substrate between the source and drain terminals, and a floating gate disposed between the control gate and the semiconductor substrate, which is electrically isolated from the control gate by a charge trapping barrier, and which is electrically isolated from the semiconductor substrate by a charge blocking barrier, at least one of the charge trapping barrier and the charge blocking barrier comprising a III-V semiconductor material, wherein the charge trapping barrier is adapted to enable selective passage of charge carriers between the control gate and the floating gate, in use, to modify the one or more bits of information stored by the memory cell, wherein the charge trapping barrier is a resonant tunnelling barrier and the passage of charge carriers between the control gate and the floating gate is by resonant tunnelling.
A method of manufacturing a memory cell for storing one or more bits of information, the method comprising the steps of:
- (a) providing a control gate, a source terminal and a drain terminal, and a semiconductor substrate between the source and drain terminals, and
- (b) providing a floating gate disposed between the control gate and the semiconductor substrate, which is electrically isolated from the control gate by a charge trapping barrier, and which is electrically isolated from the semiconductor substrate by a charge blocking barrier,
- wherein the charge trapping barrier is adapted to enable the selective passage of charge carriers between the control gate and the floating gate, in use, to modify the one or more bits of information stored by the memory cell, and at least one of the charge trapping barrier and the charge blocking barrier comprises a III-V semiconductor material, and
- wherein the charge trapping barrier is a resonant tunnelling barrier and the passage of charge carriers between the control gate and the floating gate is by resonant tunnelling.
Dependencies are inferred from the claim text.