Integrating standard-gate and extended-gate nanosheet transistors on the same substrate

A method of fabricating semiconductor devices, the method comprising:

• performing fabrication operations to form nanosheet field effect transistor devices on a substrate, wherein the fabrication operations include:
• forming a first nanosheet transistor device and a second nanosheet transistor device on a substrate;
• wherein forming the first nanosheet transistor comprises:
• forming a first sacrificial nanosheet over a first region of a substrate, the first sacrificial nanosheet having a first sacrificial nanosheet thickness dimension;
• forming a first channel nanosheet over the first sacrificial nanosheet and above the first region of the substrate, the first channel nano sheet having a first channel nanosheet thickness dimension;
• forming a second sacrificial nanosheet over a first region of the first channel nanosheet and above the first region of the substrate, the second sacrificial nanosheet having a second sacrificial nanosheet thickness dimension;
• forming a second channel nanosheet over a first region of the second sacrificial nanosheet and above the first region of the substrate, the second channel nanosheet having a second channel nanosheet thickness dimension;
• forming a third sacrificial nanosheet over a first region of the second channel nanosheet and above the first region of the substrate, the third sacrificial nanosheet having a third sacrificial nanosheet thickness dimension;
• forming a third channel nanosheet over a first region of the third sacrificial nanosheet and above the first region of the substrate, the third channel nanosheet having a third channel nanosheet thickness dimension;
• removing the second sacrificial nanosheet, the third sacrificial nanosheet, and the portion of the first sacrificial nanosheet that is above the first region of the nanosheet;
• forming a first gate oxide in the spaces that were occupied by the second sacrificial nanosheet and the portion of the first sacrificial nanosheet that is above the first region of the substrate, the first gate oxide comprising a first gate oxide thickness dimension;
• wherein forming the second nanosheet transistor comprises:
• forming the first sacrificial nanosheet over a second region of the substrate, the first sacrificial nanosheet having the first sacrificial nanosheet thickness dimension;
• forming the first channel nanosheet over the first sacrificial nanosheet and above the second region of the substrate, the first channel nanosheet having the first channel nanosheet thickness dimension;
• forming a fourth sacrificial nanosheet over a second region of the first channel nanosheet and above the second region of the substrate, the fourth sacrificial nanosheet having a second sacrificial nanosheet thickness dimension;
• forming the second channel nanosheet over the second sacrificial nanosheet and above the second region of the substrate, the second channel nanosheet having a second channel nanosheet thickness dimension;
• removing the fourth sacrificial nanosheet and the portion of the first sacrificial nanosheet that is above the second region of the nanosheet;
• and
• forming a second gate oxide in the spaces that were occupied by the fourth sacrificial nanosheet and the portion of the first sacrificial nanosheet that was over the second region of the substrate, the second gate oxide comprising a first gate oxide thickness dimension.

A set of nanosheet field effect transistor devices formed on a substrate, the nanosheet field effect transistor devices comprising:

• a first nanosheet transistor device and a second nanosheet transistor device formed on the substrate;
• wherein the first nanosheet transistor comprises:
• a first plurality of channel nanosheets comprising a bottommost first channel nanosheet and a topmost second channel nanosheet;
• a first gate region having a first gate dielectric and a first gate metal formed therein, the first gate region having a first gate region thickness dimension;
• and
• a second gate region having a second gate dielectric and a second gate metal formed therein, the second gate region having a second gate region thickness dimension;
• wherein the second nanosheet transistor comprises:
• a second plurality of channel nanosheets comprising a bottommost third channel nanosheet and a topmost fourth channel nanosheet;
• a third gate region having a third gate dielectric and a first gate metal formed therein, the first gate region having a first gate region thickness dimension;
• and
• a fourth gate region having a fourth gate dielectric and a fourth gate metal formed therein, the fourth gate region having a fourth gate region thickness dimension;
• wherein:
• the fourth gate region thickness dimension is greater than the second gate region thickness dimension;
• and
• the second gate dielectric thickness dimension is greater than the first gate dielectric thickness dimension.