Compiler optimization to reduce the control flow divergence
AssigneeIntel Corporation
InventorRahul P. Sathe
Life of this patent
Estimating the term…
Abstract
In one embodiment a graphics processing system comprises a graphics processor having execution logic and shared memory and a shader compiler unit to compile a shader program for execution by the execution logic of the graphic processor, wherein the shader is to optimize the shader program during the compile, wherein to optimize the shader program includes to convert a divergent block of parallel instructions into a divergent block and a non-divergent block of instructions.
Claims20
A graphics processing system comprising:
- a graphics processor execution logic and shared memory;
- a shader compiler unit to compile a shader program for execution by a single instruction multiple data (SIMD) logic of the execution logic of the graphic processor, the shader compiler further to optimize the shader program during the compile, wherein to optimize the shader program at compile time includes to determine if any unstructured control flow having multiple entries or exits exists within the shader program and to convert any unstructured control flow including a divergent control flow block of parallel instructions into a divergent control flow block and a non-divergent control flow block of instructions to enhance utilization of the SIMD logic of the execution logic, wherein the shader compiler is to further optimize by parallelizing along different axis of parallelism for each block of the control flow to indicate that divergent code flows are executed serially in parallel by single instruction multiple data (SIMD) logic such that no divergence occurs within each block of the control flow, wherein divergence for the control flow is defined as including multiple, mutually exclusive control flow paths.
A computer-implemented method at a graphics processing system, the method comprising:
- identifying inputs for instructions in each block of control flow for a shader program;
- allocating a buffer to store inputs for threads in a thread group of the shader program;
- convert instructions for each block of the control flow to atomically increment a counter for each input of the block;
- synchronize the shader thread groups associated with each block;
- and
- parallelize along different axis of parallelism for each block of the control flow to indicate that divergent code flows are executed in parallel by single instruction multiple data (SIMD) logic such that no divergence occurs within each block of the control flow, wherein divergence for the control flow is defined as including multiple, mutually exclusive control flow paths.
A non-transitory computer-readable storage medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform operations comprising:
- identifying inputs for instructions in each block of control flow for a shader program;
- allocating a buffer to store inputs for threads in a thread group of the shader program;
- convert instructions for each block of the control flow to atomically increment a counter for each input of the block;
- synchronize the shader thread groups associated with each block;
- and
- for each block of the control flow, parallelize along a different axis of parallelism to indicate that divergent code flows are executed in parallel by single instruction multiple data (SIMD) logic such that no divergence occurs within each block of the control flow, wherein divergence for the control flow is defined as including multiple, mutually exclusive control flow paths.
Dependencies are inferred from the claim text.