US 10,242,151 B2Granted

Method and system for computer-aided design of radiation-hardened integrated circuits

AssigneeTallannQuest LLC

InventorEmily Ann Donnelly

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Abstract

A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.

Claims16

Dependent claims

A computer-implemented method for designing a radiation-hardened integrated circuit comprising the steps of:

generating at least one device model for use in a circuit simulation, said device model having at least one parameter with a value that varies as a function of Total Ionizing Dose (TID);
entering a schematic of a circuit, said circuit comprising at least a portion of an integrated circuit, and a list of requirements comprising at least a radiation-hardness requirement, said radiation-hardness requirement comprising a requirement that the circuit meet a predetermined specification upon exposure to ionizing radiation at a specified first TID level;
performing a layout of the circuit;
assessing a rad-hard performance of the circuit, wherein said step of assessing comprises using a computing system to run a circuit simulation that uses said device model, said rad-hard performance characterized by a second TID level, upon exposure to which the circuit, if fabricated as laid out, will fail to meet the predetermined specification;
suggesting a change to the layout if the second TID level determined in assessing the rad-hard performance does not meet or exceed the first TID level specified in the radiation-hardness requirement;
and
changing the layout in response to the suggested change, whereby a design for the circuit is produced that, if fabricated, will meet the radiation-hardness requirement.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/691,969Filed 31 Aug 2017 · division
Priority: 7 Apr 2014
Published: US 2018/0096096 A15 Apr 2018
Granted: 26 Mar 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
G06F 30/367
Circuit design at the analogue level: design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE],…
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F
Computing and data processing

Family

Application61/976,482Us provisional application · filed 7 Apr 2014
Application14/681,028Parent of this continuation · filed 7 Apr 2015
Application15/382,914Parent of this division · filed 19 Dec 2016
US 9,569,583 B2Parent of this continuation · filed 14 Feb 2017
US 2018/0096096 A1Pre-grant publication · published 5 Apr 2018
US 9,779,203 B2Parent of this division
Application15/382,914Parent of this continuation
US 2015/0286772 A1Published application
US 2017/0098028 A1Published application
US 10,242,151 B2This patent

From the US filing history. Foreign family members aren’t listed.