Multilevel via placement with improved yield in dual damascene interconnection
AssigneeTexas Instruments Incorporated
InventorQi-Zhong Hong
Life of this patent
Estimating the term…
Abstract
A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect using via priority groups.
Claims19
A non-transitory computer-readable medium for modifying a layout of an integrated circuit, comprising instructions stored thereon, that when executed on a processor, perform the steps of:
- retrieving a top via layer and a bottom via layer of the integrated circuit wherein the top via layer and the bottom via layer are adjacent an intermediate interconnect level;
- performing a first modification of at least one of the top via layer and the bottom via layer to form an R-stack;
- and
- subsequently, storing the top via layer and the bottom via layer with the first modification.
A non-transitory computer-readable medium for modifying a layout of an integrated circuit, comprising instructions stored thereon, that when executed on a processor, perform the steps of:
- loading via group priority into a computer system wherein a highest priority via group contains vias which carry a highest current density during operation of the integrated circuit;
- selecting the via group with the highest priority;
- loading a top via group and a bottom via group for vias in the highest priority via group wherein the vias in the top and the bottom via groups are both connected to an intermediate interconnect layer;
- and
- performing a first modification to the top and the bottom via groups to form an R-stack.
A non-transitory computer-readable medium comprising instructions stored thereon, that when executed on a processor, form a modified layout of an integrated circuit by performing the steps of:
- retrieving a top via layer and a bottom via layer of the integrated circuit wherein the top via layer and the bottom via layer are adjacent an intermediate interconnect level;
- identifying a first top via of the top via layer and a first bottom via of the bottom via layer in a neighborhood of the first top via;
- using the processor, creating an R-stack by moving one of the first top via and the first bottom via so that the distance from a center of the first top via to the center of the first bottom via is less than or equal to a half-height diameter of the first top via.
Dependencies are inferred from the claim text.