US 10,242,144 B1Granted

Methods for minimizing logic overlap on integrated circuits

AssigneeAltera Corporation

InventorsSaurabh Adya, Mahesh A. Iyer, Love Singhal

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Abstract

Configuration data for an integrated circuit may be generated using logic design equipment to implement an optimal design on the integrated circuit. Implementing the optimal design may include placing hardware resources within the integrated circuit to decrease or remove overlaps between corresponding hardware resources. A given hardware resource may be defined as a rectangular region, an adjacent hardware resource may be defined as another rectangular region, and together, they may be defined as a hardware resource pair. The hardware resource pair may define an overlap region, with which a cost function may be associated. The cost function may be minimized in conjunction with other types of cost functions using a solver. The solver may generate coordinates that minimize or remove overlap to be implemented in the optimal design.

Claims13

Dependent claims

A method of using logic design computing equipment to generate configuration data for loading onto an integrated circuit, wherein the integrated circuit implements a logic design when loaded with the configuration data, the method comprising:

with the logic design computing equipment, identifying a first rectangular region of circuit elements within the logic design by identifying a first set of coordinates corresponding to at least two corners of the first rectangular region of circuit elements;
with the logic design computing equipment, identifying a second rectangular region of circuit elements within the logic design by identifying a second set of coordinates corresponding to at least two corners of the second rectangular region of circuit elements;
with the logic design computing equipment, identifying an overlap region between the first and second identified rectangular regions of circuit elements;
with the logic design computing equipment, defining a cost function based on the identified overlap region;
with the logic design computing equipment, minimizing the cost function to generate placement coordinates for the first and second rectangular regions of circuit elements;
with the logic design computing equipment, placing the first and second rectangular regions of circuit elements at the generated placement coordinates in the logic design to generate a placed logic design;
and
with the logic design computing equipment, generating the configuration data based on the placed logic design;
loading the configuration data onto the integrated circuit;
and
with the integrated circuit, implementing the logic design after being loaded with the configuration data.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/338,134Filed 28 Oct 2016
Granted: 26 Mar 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 30/343
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: logical level
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement