Reset sequencing for reducing noise on a power distribution network

A tangible, non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to:

• receive a first circuit design for an integrated circuit device;
• identify each reset endpoint instantiated in the first circuit design;
• generate reset sequencing logic included in a reset sequencer when at least one instantiated reset endpoint is identified, wherein the reset sequencing logic reduces noise in a power distribution network shared by one or more circuitry components of the integrated circuit device by scheduling the reset endpoints of the circuitry components so that two reset endpoints do not occur substantially simultaneously;
• insert the reset sequencer into the first circuit design during compilation to create a second circuit design;
• and
• implement the second circuit design on the integrated circuit device.

An integrated circuit device comprising:

• a memory storing compilation software;
• and
• a processor that executes the compilation software to:
• receive a first circuit design for a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC);
• identify each reset endpoint instantiated in the first circuit design;
• generate reset sequencing logic included in a reset sequencer when at least one instantiated reset endpoint is identified, wherein the reset sequencing logic reduces noise in a power distribution network shared by one or more circuitry components of the FPGA or ASIC by scheduling reset endpoints for the circuitry components a separation time apart from each other;
• insert the reset sequencer into the first circuit design to create a second circuit design;
• establish reset request and reset acknowledge connections between each reset endpoint and the reset sequencer without user intervention;
• and
• implement the second circuit design on the FPGA or ASIC.