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US 10,242,140 B2Granted
Layout of large block synthesis blocks in integrated circuits
AssigneeInternational Business Machines Corporation
InventorsHarry Barowski, Harald D. Folberth, Joachim Keinert, Sourav Saha
Life of this patent
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Abstract
Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.
Claims18
A computer system comprising:
- a memory;
- and
- one or more processors in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
- generating, by the one or more processors, a layout of an integrated circuit chip area from a description of an integrated circuit (IC), the description comprising a register-transfer-level (RTL) design, wherein the RTL design is partitioned into large blocks for synthesis of large block synthesis (LBS) blocks, the description of the IC further comprising a first floorplan for the IC, wherein LBS blocks to be synthesized are assigned to respective rectilinear shapes in the first floorplan and said rectilinear shapes do not overlap each other the generating comprising:
- selecting a pair of the LBS blocks having their cells synthesized and placed according to the RTL design and the first floorplan and routed according to the RTL design;
- generating a further floorplan in which the rectilinear shapes of the selected LBS blocks overlap each other and their overlap constitutes an overlap shape comprising at least a portion of the first border shape and at least a portion of the second border shape, wherein a cross-over shape comprises the first border shape and the second border shape;
- generating layouts of the selected LBS blocks, the generating comprising executing synthesis and placement of their cells according to the RTL design and the further floorplan and routing internal interconnects of each of the selected LBS blocks according to the RTL design;
- based on a first case in which the first value is less than the first target density value and the second value is greater than or equal to the second target density value, updating the further floorplan such that the overall geometric area assigned to the one of the selected LBS blocks in the cross-over shape is increased;
- and
- based on a second case in which the second value is less than the first target density value and the first value is greater than or equal to the second target density value, updating the further floorplan such that the overall geometric area assigned to the other one of the selected LBS blocks in the cross-over shape is increased;
- and
- fabricating an IC chip utilizing the layout.
9 more elements
A computer program product comprising:
- a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
- generating, by the one or more processors, a layout of an integrated circuit chip area from a description of an integrated circuit (IC), the description comprising a register-transfer-level (RTL) design, wherein the RTL design is partitioned into large blocks for synthesis of large block synthesis (LBS) blocks, the description of the IC further comprising a first floorplan for the IC, wherein LBS blocks to be synthesized are assigned to respective rectilinear shapes in the first floorplan and said rectilinear shapes do not overlap each other, the generating comprising:
- selecting a pair of the LBS blocks having their cells synthesized and placed according to the RTL design and the first floorplan and routed according to the RTL design;
- generating a further floorplan in which the rectilinear shapes of the selected LBS blocks overlap each other and their overlap constitutes an overlap shape comprising at least a portion of the first border shape and at least a portion of the second border shape, wherein a cross-over shape comprises the first border shape and the second border shape;
- generating layouts of the selected LBS blocks, the generating comprising executing synthesis and placement of their cells according to the RTL design and the further floorplan and routing internal interconnects of each of the selected LBS blocks according to the RTL design;
- based on a first case in which the first value is less than the first target density value and the second value is greater than or equal to the second target density value, updating the further floorplan such that the overall geometric area assigned to the one of the selected LBS blocks in the cross-over shape is increased;
- and
- based on a second case in which the second value is less than the first target density value and the first value is greater than or equal to the second target density value, updating the further floorplan such that the overall geometric area assigned to the other one of the selected LBS blocks in the cross-over shape is increased;
- and
- fabricating an IC chip utilizing the layout.
7 more elements
Dependencies are inferred from the claim text.