Method of automatic synthesis of circuits, device and computer program associated therewith

A device to synthesize a circuit, the device comprising:

• a producer, wherein the producer is authorized to execute a unique producer process, to write data in a channel of a network of regular processes interconnected with the aid of channels wherein each channel includes an addressable physical memory;
• a consumer, wherein the consumer is authorized to execute a unique consumer process, to read data in the channel;
• and
• a synchronization unit associated with the channel to collect, prior to the launch of each new iteration by the producer process of the channel, a value of the new iteration of the producer process, and to collect, prior to the launch of each new iteration by the consumer process of the channel, an iteration value of the consumer process;
• the synchronization unit, following the collection of the value of the new iteration of the producer and consumer process respectively, determines to authorize or freeze the implementation of the new iteration of the producer and consumer process respectively, based on a comparison of a producer execution position determined according to the new iteration value collected from the producer, and a consumer execution position determined according to the iteration value collected from the consumer process, wherein the circuit is synthesized based on the authorizing and freezing of the implementation of the producer iteration and the authorizing and freezing of the implementation of the consumer iteration and a field-programmable gate array or chip is fabricated based on the synthesis of the circuit.

A synthesized circuit for fabricating a field-programmable gate array or chip, the synthesized circuit comprising:

• a network of regular processes interconnected with the aid of channels, wherein each channel includes an addressable physical memory, each of said processes in each iteration of an iteration domain with which it is associated performs at least one data read in a channel and/or one data write in a channel, and a sequencing function for each iteration value of each process, determines an execution position of the process selected in a time-sequenced set of execution positions;
• a producer associated with each channel and authorized to execute a unique producer process to write data in the channel;
• a consumer associated with each channel and authorized to execute a unique consumer process to read data in said channel;
• and
• a synchronization unit associated with each channel to collect, prior to the launch of each new iteration by the producer process of the channel, a value of a new iteration of the producer process, and to collect, prior to the launch of each new iteration by the consumer process of the channel, an iteration value of the consumer process, the synchronization unit, following the collection of the value of a new iteration of the producer and consumer process respectively determines to authorize or freeze the new iteration of said producer and consumer process respectively, on the basis of a comparison of a producer execution position determined according to the new iteration value collected from a producer, and a consumer execution position determined according to the last iteration value collected from the consumer;
• wherein a field-programmable gate array or chip is fabricated from the synthesized circuit.