US 10,242,135 B2Granted

Testbench chaining for multiple blocks in hierarchical circuit design

AssigneeSynopsys, Inc.

InventorsGajanan Madhukarrao Joshi, Jonathan Lee Sanders, Donald John Oriordan, Ruben Grigoryan, Hui Xu

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Abstract

A selection of a source testbench is received from a user. The source testbench includes a description of one or more source parameters, a description of one or more source measurements, and a plurality of source entries, each of the source entries including a value for each of the one or more source parameters and each of the one or more source measurements. Furthermore, a selection of a destination testbench is received. The destination testbench includes a description of one or more destination parameters and a plurality of destination entries including a value for each of the one or more destination parameters. One or more source entries are matched with a destination entry. One or more source measurements of the matched one or more source entries are aggregated based on an aggregation function, and the aggregated source measurements are mapped to the matched source entry.

Claims20

Dependent claims

A method comprising:

receiving a selection of a source testbench, the source testbench including:
a description of one or more source parameters for testing of a source circuit block,
a description of one or more source measurements from the testing of the source circuit block, and
a plurality of source entries, each of the source entries including a value for each of the one or more source parameters and each of the one or more source measurements;
receiving a selection of a destination testbench, the destination testbench including:
a description of one or more destination parameters, and
a plurality of destination entries including a value for each of the one or more destination parameters;
matching one or more source entries from the plurality of source entries with a destination entry from the plurality of destination entries, the matching performed by comparing:
the value of the one or more source parameters of each of the source entries, and
the value of the one or more destination parameters of each of the destination entries;
aggregating the value of one or more of the source measurements of the matched one or more source entries using an aggregation function to obtain one or more aggregated source measurement values;
and
mapping the one or more aggregated source measurement values to the matched destination entry.

10 more elements

A method comprising:

matching one or more source entries from a plurality of source entries of a source testbench with a destination entry from a plurality of destination entries of a destination testbench, the matching performed by comparing:
a value of one or more source parameters of each of the plurality of source entries, and
a value of one or more destination parameters of each of the plurality of destination entries;
aggregating the value of one or more of the source measurements of the matched one or more source entries using an aggregation function to obtain one or more aggregated source measurement values;
and
mapping the one or more aggregated source measurement values to the matched destination entry.

3 more elements

A non-transitory computer readable storage medium storing instructions, the instruction when executed by a processor cause the processor to:

match one or more source entries from a plurality of source entries of a source testbench with a destination entry from a plurality of destination entries of a destination testbench, the matching performed by comparing:
a value of one or more source parameters of each of the plurality of source entries, and
a value of one or more destination parameters of each of the plurality of destination entries;
aggregate the value of one or more of the source measurements of the matched one or more source entries using an aggregation function to obtain one or more aggregated source measurement values;
and
map the one or more aggregated source measurement values to the matched destination entry.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/442,480Filed 24 Feb 2017 · us provisional application
Priority: 25 Feb 2016
Published: US 2017/0249411 A131 Aug 2017
Granted: 26 Mar 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 30/367
Circuit design at the analogue level: design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE],…
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking
G06F
Computing and data processing