Coding wave-pipelined circuits with buffering function in HDL

A method for constructing a circuit of wave-pipelining with a buffering function in HDL (hardware description language), the method comprising:

• constructing a first part of the circuit, the first part comprising at least one critical path, each critical path of the at least one critical path comprising an input register, a piece of combinational logic and an output register, the piece of combinational logic connecting the input register to the output register, a positive integer Register_number being defined to be equal to a sum of a total number of the at least one input register and a total number of the at least one output register in the circuit, the at least one critical path providing a first storage, and the first storage being able to buffer up to the positive integer Register_number of a plurality of working data;
• constructing a second part of the circuit, the second part guaranteeing that each output register of the at least one output register solely owns an output register state machine, and the output register state machine comprising three states:
• an idle state:
• the idle state indicates that an owner output register is empty on a current cycle;
• an active state:
• the active state indicates that the owner output register is an active output register, the owner output register has a working datum in the plurality of working data, and the working datum is latched on the current cycle;
• and
• a buffered state:
• the buffered state indicates that the owner output register is a buffered output register, the owner output register has a working datum in the plurality of working data, and the working datum was latched on a past cycle;
• and
• constructing a control unit that connects the first part to the second part and controls the plurality of working data travelling through the circuit without a data contamination.