US 10,241,956 B2 · Virtualizing coherent hardware accelerators

Abstract

An approach to virtualizing a coherent memory hardware accelerator is provided comprising creating a segment table for a client logical partition (LPAR), wherein a virtual address space is reserved in the segment table, receiving an Input/Output (I/O) request to use the coherent memory hardware accelerator, generating an I/O operation associated with the I/O request, wherein the I/O operation is passed to the coherent memory hardware accelerator, receiving a map request from the coherent memory hardware accelerator, creating an entry in the reserved virtual address space in the segment table, creating a hardware page table map request for mapping a memory address associated with the client LPAR and returning the reserved virtual address space to the coherent memory hardware accelerator, wherein the coherent memory hardware accelerator has remote direct memory access to memory associated with the client LPAR for performing an acceleration of one or more processes.

Claims20

Dependent claims

A method for virtualizing a hardware accelerator that utilizes a coherent accelerator processors interface (CAPI), the method comprising:

creating, by one or more processors of a virtual Input/Output server (VIOS), a segment table for a client logical partition (LPAR), wherein a virtual address space is reserved in the segment table;
receiving, by one or more processors of the VIOS, an Input/Output (I/O) request to utilize a hardware accelerator;
generating, by one or more processors of the VIOS, an I/O operation associated with the I/O request, wherein the I/O operation is passed to the hardware accelerator;
receiving, by one or more processors of the VIOS, a map request from the hardware accelerator;
creating, by one or more processors of the VIOS, an entry in the reserved virtual address space in the segment table;
creating, by one or more processors of the VIOS, a hardware page table map request for mapping a physical memory address associated with I/O buffer pages of the client LPAR;
and
identifying, by one or more processors of the VIOS, the reserved virtual address space to the hardware accelerator, wherein the hardware accelerator utilizes remote direct memory access between memory associated with the client LPAR and the hardware accelerator to perform an acceleration of one or more processes.

5 more elements

A computer program product for a hardware accelerator that utilizes a coherent accelerator processors interface (CAPI), the computer program product comprising:

one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions readable/executable by one or more computer processors, the program instructions comprising:
program instructions to create, utilizing one or more processors of a virtual Input/Output server (VIOS), a segment table for a client logical partition (LPAR), wherein a virtual address space is reserved in the segment table;
program instructions to receive, utilizing one or more processors of the VIOS, an Input/Output (I/O) request to utilize a hardware accelerator;
program instructions to generate, utilizing one or more processors of the virtual VIOS, an I/O operation associated with the I/O request, wherein the I/O operation is passed to the hardware accelerator;
program instructions to receive, utilizing one or more processors of the VIOS, a map request from the hardware accelerator;
program instructions to create, utilizing one or more processors of the VIOS, an entry in the reserved virtual address space in the segment table;
program instructions to create, utilizing one or more processors of the VIOS, a hardware page table map request for mapping a physical memory address associated with I/O buffer pages of the client LPAR;
and
program instructions to identify, utilizing one or more processors of the VIOS, the reserved virtual address space to the hardware accelerator, wherein the hardware accelerator utilizes remote direct memory access between memory associated with the client LPAR and the hardware accelerator to perform an acceleration of one or more processes.

6 more elements

A computer system for virtualizing a hardware accelerator that utilizes a coherent accelerator processor interface (CAPI), the computer system comprising:

one or more computer processors;
one or more computer readable storage media;
program instructions stored on the one or more computer readable storage media for execution by at least one of the one or more processors, the program instructions comprising:
program instructions to create, utilizing one or more processors of a virtual Input/Output server (VIOS), a segment table for a client logical partition (LPAR), wherein a virtual address space is reserved in the segment table;
program instructions to receive, utilizing one or more processors of the VIOS, an Input/Output (I/O) request to utilize a hardware accelerator;
program instructions to generate, utilizing one or more processors of the VIOS, an I/O operation associated with the I/O request, wherein the I/O operation is passed to the hardware accelerator;
program instructions to receive, utilizing one or more processors of the VIOS, a map request from the hardware accelerator;
program instructions to create, utilizing one or more processors of the VIOS, an entry in the reserved virtual address space in the segment table;
program instructions to create, utilizing one or more processors of the VIOS, a hardware page table map request for mapping a memory address associated with the client LPAR;
and
program instructions to identify, utilizing one or more processors of the VIOS, the reserved virtual address space to the hardware accelerator, wherein the hardware accelerator utilizes remote direct memory access between memory associated with the client LPAR and the hardware accelerator to perform an acceleration of one or more processes.

8 more elements

Dependencies are inferred from the claim text.

Virtualizing coherent hardware accelerators

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Virtualizing coherent hardware accelerators

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Abstract

Claims20