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US 10,241,952 B2Granted
Throttling integrated link
AssigneeIntel Corporation
InventorsRavi Rajwar, Robert A. Mayer, Stephan J. Jourdan, Lily Pao Looi
Life of this patent
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Abstract
Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
Claims21
A integrated circuit device comprising:
- a processor;
- and
- an Integrated Input/Output (IIO) logic coupled to the processor,
- wherein a signal is to cause throttling of a link coupled between the IIO and an Input/Output (IO) device, wherein the link is one of a transmit link or a receive link, wherein throttling of the transmit link is to be performed by an on or off modulation, wherein the transmit link remains in an off state for a first duration, wherein the transmit link is to transmit an acknowledgement signal in response to receiving a packet and within a second duration from receiving the packet, wherein an upper link layer logic of the processor is to provide link support for upper link layer communication with the IIO logic, wherein separation of read and write pointers is configurable to account for clock skew differences between the upper link layer logic and the IIO logic, wherein the read and write pointers are to be reset in response to an indication that the processor and the IIO logic are awake.
1 more element
A method comprising:
- generating a signal to cause throttling of a link coupled between an IIO logic and an Input/Output (IO) device in response to detection of a temperature value at the link, wherein the link is to comprise a transmit link or a receive link,
- wherein throttling of the transmit link is performed by an on or off modulation, wherein throttling of the transmit link is performed by an on or off modulation, wherein the transmit link remains in an off state for a first duration, wherein the transmit link transmits an acknowledgement signal during an on state in response to receiving a packet on the receive link and within a second duration from receiving the packet, wherein an upper link layer logic provides link support for upper link layer communication with the IIO logic, wherein separation of read and write pointers is configurable to account for clock skew differences between the upper link layer logic and the IIO logic, wherein the read and write pointers are reset in response to an indication that a processor and the IIO logic are awake.
A system comprising:
- a system memory to store data;
- a processor to access the stored data;
- and
- an Integrated Input/Output (IIO) logic coupled to the processor,
- wherein a signal causes throttling of a point-to-point a link coupled between the IIO and an Input/Output (IO) device,
- wherein data is communicated between the system memory and one or more I/O devices via the IIO logic, wherein the link is a transmit link or a receive link, wherein throttling of the transmit link is to be performed by an on or off modulation, wherein throttling of the transmit link is performed by an on or off modulation, wherein the transmit link remains in an off state for a first duration, wherein the transmit link transmits an acknowledgement signal during an on state in response to receiving a packet on the receive link and within a second duration from receiving the packet, wherein an upper link layer logic of the processor is to provide link support for upper link layer communication with the IIO logic, wherein separation of read and write pointers is configurable to account for clock skew differences between the upper link layer logic and the IIO logic, wherein the read and write pointers are to be reset in response to an indication that the processor and the IIO logic are awake.
3 more elements
Dependencies are inferred from the claim text.