Hardware-based virtual machine communication

A system, comprising:

• a first interface device to support direct memory access (DMA) data transfers by a first virtual machine (VM);
• and
• a VM-to-VM communication accelerator circuit, communicatively coupled to a processor to execute the first VM, the VM-to-VM communication accelerator circuit comprising:
• a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM;
• and
• a direct memory access (DMA) descriptor processing circuit to:
• process, using a working queue associated with the primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM;
• and
• execute, using the first interface device, the DMA data transfer based on the access permission.

A method comprising:

• receiving, by an accelerator circuit communicatively coupled to a processor, a direct memory access (DMA) descriptor issued by a first virtual machine (VM) executing on the processor, the DMA descriptor specifying a DMA data transfer between the first virtual machine and a second virtual machine using a first interface device associated with the processor;
• determining, based on an access control table (ACT), an access permission from the first VM to the second VM, wherein the accelerator circuit comprises a register to store a reference to a physical function (PF) associated with the first interface device, and wherein the PF is associated with the ACT specifying the access permission;
• and
• executing, using the first interface device, the DMA data transfer based on the access permission.