Multi-channel DMA system with command queue structure supporting three DMA modes

An apparatus comprising:

• a context store for storing data structures to assist with processing of a plurality of active Direct Memory Access (DMA) channels;
• a plurality of command queue FIFO memories that store command sequences associated with one or more virtual DMA channels and that are connected across an arbiter and dispatcher circuit to the context store;
• a bus interface suitably coupled to the context store and the plurality of command queue FIFO memories;
• and
• a DMA controller suitably coupled to the context store, plurality of command queue FIFO memories, and the bus interface, the DMA controller comprising a plurality of virtual DMA channel registers for supporting a plurality of virtual DMA channels, an arbiter, and a lookup table for associating one or more of the plurality of virtual DMA channels with one or more of the plurality of command queue FIFO memories.

An electronic device comprising:

• a processor and memory connected for access to an interconnect;
• a multi-channel direct memory access (DMA) interface coupled to the interconnect and comprising a command queue FIFO memory for storing command sequences to support simultaneous management of a plurality of direct memory access (DMA) channels in a plurality of different DMA modes comprising a direct configuration DMA mode, a link list configuration DMA mode, and a program configuration DMA mode;
• a context store for storing data structures to assist with processing of a plurality of active DMA channels;
• a bus interface suitably coupled to the context store and the command queue FIFO memory;
• and
• a DMA controller suitably coupled to the context store, command queue FIFO memory, and the bus interface, the DMA controller comprising a plurality of virtual DMA channel registers for supporting a plurality of virtual DMA channels, an arbiter, and a lookup table for associating one or more of the plurality of virtual DMA channels with one or more FIFO registers in the command queue FIFO memory.