Memory channel that supports near memory and far memory access
AssigneeIntel Corporation
InventorsBill Nale, Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
Life of this patent
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Abstract
A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol
Claims17
A memory controller, comprising:
- an interface to a memory channel that supports double data rate (DDR) volatile memory accesses;
- circuitry to limit outstanding write requests directed by the memory controller to a DIMM that is coupled to the memory channel, the circuitry to maintain a credit count and to decrement the credit count with a next write request, the circuitry to increment the credit count in response to the memory controller's reception of credit feedback information sent by the DIMM to the memory controller.
A DIMM, comprising:
- non volatile memory;
- a write buffer to temporarily store write requests directed to the DIMM by a memory controller;
- circuitry to send updates to the memory controller regarding the write buffer's amount of available storage space.
A method, comprising:
- sending read requests to a first DIMM having volatile memory that is plugged into a memory channel, the sending of the read requests being performed according to an industry standard DDR protocol;
- sending write requests to a second DIMM having non volatile memory that is also plugged into the channel and maintaining a credit count commensurate with the sending that indicates how much write buffer space is available on the second DIMM, the sending of the write requests to cease if the credit count reaches a level that indicates insufficient write buffer space is available to receive a next write request.
Dependencies are inferred from the claim text.