Output data path for non-volatile memory

A system comprising:

• one or more non-volatile memory elements, a non-volatile memory element comprising:
• a plurality of buffer stages for output data of the non-volatile memory element;
• a parallel-in serial-out (PISO) component that receives data from a buffer stage via PISO input lines and outputs the data in a series of transfers controlled according to a read enable clock signal, via PISO output lines, wherein the PISO component comprises more PISO input lines than PISO output lines;
• and
• an early read pointer and a later read pointer, wherein an internal controller for the non-volatile memory element updates the early read pointer and the later read pointer in response to different portions of the read enable clock signal, such that the internal controller couples an early portion of the buffer stage to a first subset of the PISO input lines by updating the early read pointer to point to the buffer stage, and couples a later portion of the buffer stage to a second subset of the PISO input lines by updating the later read pointer to point to the buffer stage.

An apparatus comprising:

• means for buffering output data of a non-volatile memory element in buffer stages of a buffer stage width;
• means for outputting data at an output data width narrower than the buffer stage width in a series of transfers controlled according to a clock signal, the data received from a portion of a buffer stage of the buffer stages in response to an internal controller for the non-volatile memory element updating a read pointer to point to the buffer stage;
• and
• means for coupling buffer stage portions to the means for outputting data, the means for coupling comprising two or more read pointers, the internal controller updating the two or more read pointers at different times in response to different portions of the clock signal.