Selecting a default page size in a variable page size TLB

#Many computing devices use a virtual memory technique for handling data accesses by programs being executed on the devices. A virtual memory page-translation mechanism enables system software to create separate address spaces for each process or application. These address spaces are known as virtual address spaces. The system software uses the paging mechanism to selectively map individual pages of physical memory into the virtual address space using a set of hierarchical address-translation tables known collectively as page tables. Virtual memory can be implemented with any processor, including, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), and an accelerated processing unit (APU).

#When data is accessed by a program, a block of memory of a given size (e.g., 4 kB) that includes the data, called a “page” of memory, is copied from mass storage (e.g., a disk drive or semiconductor memory) to an available physical location in a main memory in the computing device. Some systems have multiple different page sizes stored in memory. Rather than having programs manage the physical locations of the pages, a memory management unit in the computing device manages the physical locations of the pages. Instead of using addresses based on the physical locations of pages (or “physical addresses”) for accessing memory, the programs access memory using “virtual addresses” in “virtual address spaces,” which are local address spaces that are specific to corresponding programs. From a program's perspective, virtual addresses indicate the actual physical addresses (i.e., physical locations) where data is stored within the pages in memory and hence memory accesses are made by programs using the virtual addresses accordingly. However, the virtual addresses do not directly map to the physical addresses of the physical locations where data is stored. Thus, as part of managing the physical locations of pages, the memory management unit translates the virtual addresses used by the programs into the physical addresses where the data is actually located. The translated physical addresses are then used to perform the memory accesses for the programs.

#To perform the above-described translations, the memory management unit uses a page table in memory that includes a set of translations from virtual addresses to physical addresses for pages stored in the memory. However, using the page table to translate virtual addresses to physical addresses is slow for various reasons (e.g., the size of the page table, the operations used to perform lookups for the translation). The computing device also includes a translation lookaside buffer (or “TLB”), which is a cache of virtual address to physical address translations that were previously acquired from the page table. Performing the translation from virtual address to physical address using the TLB is significantly faster than performing the translation using the page table. However, TLBs are typically limited in size due to constraints on the area that the TLB is allowed to occupy in the integrated circuits in which the TLB is fabricated. This means that the use of the TLB can be limited and some virtual address to physical address translations must still be performed using the page table.

#The advantages of the methods and mechanisms described herein may be better understood by referring to the following description in conjunction with the accompanying drawings, in which:

#FIG. 1 is a block diagram of one embodiment of a computing system.

#FIG. 2 is a block diagram of one embodiment of a TLB complex.

#In the following description, numerous specific details are set forth to provide a thorough understanding of the methods and mechanisms presented herein. However, one having ordinary skill in the art should recognize that the various embodiments may be practiced without these specific details. In some instances, well-known structures, components, signals, computer program instructions, and techniques have not been shown in detail to avoid obscuring the approaches described herein. It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements.

#Systems, apparatuses, and methods for selecting default page sizes in a variable page size translation lookaside buffer (TLB) are disclosed herein. In one embodiment, a system includes at least one processor, a memory subsystem, and a first TLB. The first TLB is configured to allocate a first entry for a first request responsive to detecting a miss for the first request in the first TLB. Prior to determining a page size targeted by the first request, the first TLB specifies, in the first entry, that the first request targets a page of a first page size. Responsive to determining that the first request actually targets a second page size, the first TLB reissues the first request with an indication that the first request targets the second page size. On the reissue, the first TLB allocates a second entry and specifies the second page size for the first request.

#Referring now to FIG. 1, a block diagram of one embodiment of a computing system 100 is shown. In one embodiment, computing system 100 includes system on chip (SoC) 105 coupled to memory 150. SoC 105 can also be referred to as an integrated circuit (IC). In one embodiment, SoC 105 includes processing units 175A-N of central processing unit (CPU) 165, input/output (I/O) interfaces 155, caches 160A-B, fabric 120, graphics processing unit (GPU) 130, local memory 110, and memory controller(s) 140. SoC 105 can also include other components not shown in FIG. 1 to avoid obscuring the figure. Processing units 175A-N are representative of any number and type of processing units. In one embodiment, processing units 175A-N are CPU cores. In another embodiment, one or more of processing units 175A-N are other types of processing units (e.g., application specific integrated circuit (ASIC), field programmable gate array (FPGA), digital signal processor (DSP)). Processing units 175A-N of CPU 165 are coupled to caches 160A-B and fabric 120.