Processor and method
AssigneeSamsung Electronics Co., Ltd.
InventorWoong Seo
Life of this patent
Estimating the term…
Abstract
Provided is a processor including a plurality of devices. The processor includes a source processing device configured to identify data to request from another device, and a destination processing device configured to, in response to a request for the identified data from the source processing device using credit-based flow control, transmit the identified data to the source processing device using the credit-based flow control. The source processing device includes a credit buffer used for the credit-based flow control, the credit buffer being allocable to include a cache region configured to cache the transmitted identified data received by the source processing device.
Claims16
A processor, the processor comprising:
- a source processing device configured to identify data to request from another device;
- and
- a destination processing device configured to, in response to a request for the identified data from the source processing device using credit-based flow control, transmit the identified data to the source processing device using the credit-based flow control,
- wherein the source processing device comprises a credit buffer used for the credit-based flow control, the credit buffer being allocable to include a cache region configured to cache the transmitted identified data received by the source processing device;
- wherein the source processing device further comprises:
- a request first-in first-out (FIFO) buffer configured to store a result of a tag matching determination between an address of the identified data and tags corresponding to data cached in the cache region;
- and
- a controller configured to perform control to read data cached in the cache region using a hit index, indicating which entry of the cache region includes the identified data, when the stored result of the tag matching determination is a cache hit, and to perform control to increase a current write index value for the cache region when the stored result of the tag matching determination is a cache miss.
A method of processing data using a processor, the method comprising:
- identifying, by a source processing device, data to request from another device;
- storing a result of a tag matching determination between an address of the identified data and tags corresponding to data cached in a cache region;
- transmitting, by a destination processing device, the identified data to the source processing device in response to a request for the identified data from the source processing device using credit-based flow control;
- and
- caching, in a selectively allocated cache region of a credit buffer of the source processing device, the transmitted identified data as received by the source processing device,
- wherein the caching of the transmitted identified data comprises performing control to read data cached in the cache region using a hit index, indicating which entry of the cache region includes the identified data, when the stored result of the tag matching determination is a cache hit or performing control to increase a current write index value for the cache region when the stored result of the tag matching determination is a cache miss.
Dependencies are inferred from the claim text.