Apparatus and method for implementing a multi-level memory hierarchy

An apparatus, comprising:

• a) a plurality of processing cores for executing instructions and processing data and one or more processor caches for caching instructions and data;
• b) memory controller circuitry to interface with a first level memory and a second level memory,
• the first level memory to have a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed;
• and
• the second level memory to have a second set of characteristics associated therewith, the second set of characteristics including second read and write access speeds at least one of which is relatively slower than either the first read access speed or first write access speed, respectively, non-volatility such that the second level memory maintains its content if power is removed, random access and memory subsystem addressability such that instructions or data stored therein may be randomly accessed at a granularity equivalent to that used by a memory subsystem of the apparatus;
• c) register circuitry to define selection of at least one of multiple behavioral mode options for the first level memory including a first behavioral mode option in which at least a portion of the first level memory behaves as a cache for the second level memory and a second behavioral mode option in which at least a portion of the first level memory does not behave as a cache for the second level memory.