Managing an effective address table in a multi-slice processor
AssigneeInternational Business Machines Corporation
InventorsAkash V. Giri, David S. Levitan, Mehul Patel, Albert J. Van Norstrand, Jr.
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Abstract
Methods and apparatus for managing an effective address table (EAT) in a multi-slice processor including receiving, from an instruction sequence unit, a next-to-complete instruction tag (ITAG); obtaining, from the EAT, a first ITAG from a tail-plus-one EAT row, wherein the EAT comprises a tail EAT row that precedes the tail-plus-one EAT row; determining, based on a comparison of the next-to-complete ITAG and the first ITAG, that the tail EAT row has completed; and retiring the tail EAT row based on the determination.
Claims7
A method of managing an effective address table (EAT), the method comprising:
- receiving, by EAT management logic of an instruction fetch unit from an instruction sequence unit, a next-to-complete instruction tag (ITAG);
- obtaining, from the EAT, a first ITAG from a tail-plus-one EAT row, wherein the EAT comprises a tail EAT row that precedes the tail-plus-one EAT row;
- and wherein each EAT row comprises a starting effective address, an ending effective address, and a first ITAG in a range of ITAG assigned to internal operations generated from processor instructions stored at a range of effective addresses defined by the starting effective address and the ending effective address;
- determining, based on a comparison of the next-to-complete ITAG and the first ITAG, that the tail EAT row has completed;
- and
- retiring the tail EAT row based on the determination, thereby retiring one or more effective address of the tail EAT row, wherein retiring the tail EAT row further comprises freeing a range of ITAGs associated with the tail EAT row for reassignment to newly decoded instructions.
Dependencies are inferred from the claim text.