Tracking pipelined activity during off-core memory accesses to evaluate the impact of processor core frequency changes

A system for tracking pipelined activity during off-core memory accesses, comprising:

• at least one processor core comprising at least one execution unit;
• at least one counter operative to track a number of cycles in which the at least one execution unit of the at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising a plurality of cycles;
• a first counter of the at least one counter operative to track each cycle of the plurality of cycles during which none of the at least one execution unit is finishing execution and the at least one thread of the at least one processor core is waiting on at least one off-core memory access;
• a second counter of the at least one counter operative to track each cycle of the plurality of cycles during which none of the at least one execution unit is busy and the at least one thread of the at least one processor core is waiting on at least one off-core memory access;
• and
• a controller for evaluating an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions tracked in the at least one counter during the interval.

A computer program product for tracking pipelined activity during off-core memory accesses, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:

• track, by the processor, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core of the processor is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising a plurality of cycles by:
• tracking in a first counter of the at least one counter, each cycle of the plurality of cycles during which none of the at least one execution unit is finishing execution and the at least one thread of the at least one processor core is waiting on at least one off-core memory access;
• and
• tracking in a second counter of the at least one counter, each cycle of the plurality of cycles during which none of the at least one execution unit is busy and the at least one thread of the at least one processor core is waiting on at least one off-core memory access;
• and
• evaluate, by the processor, an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions tracked in the at least one counter during the interval.