System, apparatus and method for multi-kernel performance monitoring in a field programmable gate array

A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

• receiving kernel registration information of a first kernel in a hardware monitor circuit of a field programmable gate array (FPGA), the kernel registration information including programming information for a plurality of performance monitors of a hardware performance monitoring circuit of the FPGA;
• registering at least a portion of the programming information in a monitoring table of the FPGA to associate the plurality of performance monitors with the first kernel;
• and
• updating a first performance monitor of the plurality of performance monitors responsive to a first event during execution of the first kernel on the FPGA, based at least in part on the programming information.

A computing system comprising:

• a field programmable gate array (FPGA) comprising:
• hardware programmable logic to execute a first kernel associated with an application to execute on a processor;
• a hardware performance monitor circuit including a first set of performance monitors to be programmably associated with the first kernel to obtain performance information regarding interaction between the processor and the FPGA;
• and
• a hardware monitor circuit to receive kernel registration information of the first kernel and program the first set of performance monitors for association with the first kernel based on the kernel registration information to obtain monitored information corresponding to the performance information regarding the interaction between the processor and the FPGA and communicate the monitored information to the processor to enable the processor to observe and analyze the monitored information;
• and
• the processor comprising:
• a plurality of cores;
• at least one performance monitor to store the monitored information from the FPGA;
• and
• a set of registers to store metadata associated with the first set of performance monitors of the hardware performance monitor circuit of the FPGA.