Server control method and server control device

A server control method applied to a server, the server comprising at least two central processing units (CPUs) and at least two Platform Controller Hubs (PCHs), and each of the PCHs coupled to at least one of the CPUs, the method comprising:

• coupling pins of each of the at least two CPUs to a complex programmable logical device (CPLD);
• configuring labels of the CPUs using the pins coupled to the CPLD;
• marking one of the CPUs as a master CPU using the pins coupled to the CPLD;
• recording startup exception information in a register of an electrically erasable programmable read-only memory (EEPROM) of the server when a startup exception occurs, the startup exception comprising a startup exception of a basic input/output system (BIOS) caused by an exception of the master CPU, a PCH coupled to the master CPU, or a Flash that is coupled to the PCH coupled to the master CPU;
• reading the register of the EEPROM of the server when restarting the server;
• triggering the server to restart when the startup exception information is read from the register of the EEPROM of the server;
• configuring, in a restart process of the server using the pins coupled to the CPLD, a CPU or a CPU coupled to a PCH as the master CPU according to the recorded exception information, the pins coupled to the CPLD comprising a SOCKET_ID pin and an EX_LEGACY pin, a value of the SOCKET_ID pin indicating an identity of the CPU or the CPU coupled to the PCH, a value of the EX_LEGACY pin indicating whether the CPU or the CPU coupled to the PCH is a master processor or a common processor, and the CPLD configuring the CPU or the CPU coupled to the PCH as the master CPU by changing the value of the SOCKET_ID pin and the value of the EX_LEGACY pin;
• switching the PCH to a new master PCH;
• acquiring a BIOS instruction from a Flash coupled to the new master PCH;
• and
• triggering the server to restart using the BIOS instruction when the startup exception information is read from the register of the EEPROM of the server.

A server control method, comprising:

• configuring a pin of a first central processing unit (CPU) to label the first CPU as a master CPU;
• monitoring whether a startup exception occurs in the first CPU, a first Platform Controller Hub (PCH) coupled to the first CPU, or a first Flash device coupled to the first PCH;
• recording startup exception information in a register of an electrically erasable programmable read-only memory (EEPROM) of a server when the startup exception occurs, the startup exception comprising a startup exception of a basic input/output system (BIOS) caused by an exception of the master CPU, the first PCH coupled to the master CPU, or the first Flash device that is coupled to the PCH coupled to the master CPU;
• reading the register of the EEPROM of the server when restarting the server;
• reconfiguring pins of a second CPU to label the second CPU as the master CPU when the startup exception information is read from the register of the EEPROM of the server, the pins of the second CPU being reconfigured by reconfiguring a value of a SOCKET_ID pin and a value of an EX_LEGACY_SKT pin of the second CPU, the value of the SOCKET_ID pin indicating an identity of the second CPU, and the value of the EX_LEGACY pin indicating whether the second CPU is a master processor or a common processor;
• and
• restarting the server with the second CPU as the master CPU.