Estimation of error correcting performance of low-density parity-check (LDPC) codes

An apparatus comprising:

• a register to store coefficients of polynomials;
• a first circuit to calculate values of the polynomials based on values of the coefficients and a rate of erroneous bits with a selected reliability level among reliability levels associated with erroneous bits in the information retrieved from memory cells, the erroneous bits with the selected reliability level being included in the erroneous bits in the information retrieved from the memory cells;
• a second circuit to calculate a rate of codeword errors in the information retrieved from memory cells based on the values of the polynomials and a rate of erroneous bits in the information retrieved from the memory cells, wherein the reliability levels associated with the erroneous bits are based on log-likelihood ratios associated with the erroneous;
• and
• at least one hardware processor to perform a memory management operation if the rate of codeword errors exceeds a value, and the at least one hardware processor to refrain from performing the memory management operation if the rate of codeword errors does not exceed the value, wherein the at least one hardware processor includes a monitor to initiate the memory management operation based on the rate of codeword errors, and the memory management operation includes retrieving information stored in a portion of the memory cells and storing the information in another portion of the memory cells.

An apparatus comprising:

• non-volatile memory cells;
• and
• at least one hardware processor coupled to the memory cells, the at least one hardware processor including:
• a low-density parity-check (LDPC) decoding circuit to receive information retrieved from the non-volatile memory cells, the information including codewords;
• and
• a calculating circuit to calculate a rate of codeword errors in the codewords based on a rate of erroneous bits in the information and a rate of erroneous bits with a selected reliability level, the erroneous bits with the selected reliability level being a portion of the erroneous bits in the information, wherein the selected reliability level is based on one of log-likelihood ratios associated with the erroneous bits, the at least one hardware processor is to perform a memory management operation if the rate of codeword errors exceeds a value, the at least one hardware processor is to refrain from performing the memory management operation if the rate of codeword errors does not exceed the value, the at least one hardware processor includes a monitor to initiate the memory management operation based on the rate of codeword errors, and the memory management operation includes retrieving information stored in a portion of the memory cells and storing the information in another portion of the memory cells.

An apparatus comprising:

• a processor;
• and
• a solid state drive coupled to the processor, the solid stare drive including:
• non-volatile memory cells;
• and
• at least one hardware processor coupled to the memory cells, the at least one hardware processor including a low-density parity-check (LDPC) decoding circuit to receive information retrieved from memory cells, the information including codewords, and a calculating circuit to calculate a rate of codeword errors in the codewords based on a rate of erroneous bits in the information and a rate of erroneous bits with a selected reliability level, the erroneous bits with the selected reliability level being a portion of the erroneous bits in the information, wherein the selected reliability level is one of reliability levels associated with the erroneous bits, the at least one hardware processor is to perform a memory management operation if the rate of codeword errors exceeds a value, the at least one hardware processor is to refrain from performing the memory management operation if the rate of codeword errors does not exceed the value, the at least one hardware processor includes a monitor to initiate the memory management operation based on the rate of codeword errors, and the memory management operation includes retrieving information stored in a portion of the memory cells and storing the information in another portion of the memory cells.

A method comprising:

• receiving information from memory cells, the information including codewords, the codewords including data bits and low-density parity-check (LDPC) parity bits;
• calculating a rate of codeword errors in the codewords based on a rate of erroneous bits in the information and a rate of erroneous bits in the information with a selected reliability level, the erroneous bits with the selected reliability level being a portion of the erroneous hits in the information, wherein the selected reliability level is based on one of log-likelihood ratios associated with the erroneous bits;
• performing a memory management operation if the rate of codeword errors exceeds a value;
• refraining from performing the memory management operation if the rate of codeword errors does not exceed the value;
• initiating the memory management operation based on the rate of codeword errors, and
• retrieving information stored in a portion of the memory cells and storing the information in another portion of the memory cells.