Controller that receives a cyclic redundancy check (CRC) code for both read and write data transmitted via bidirectional data link

A controller, comprising:

• a bidirectional interface to transmit write data to be stored by a DRAM device and to receive read data stored by the DRAM device, the write data to include at least a write group of bits to be stored by the DRAM device and the read data to include at least a read group of bits to be received from the DRAM device;
• a cyclic redundancy check (CRC) encoder to receive the write group of bits and the read group of bits, the CRC encoder to output write error check bits corresponding the write group of bits and read error check bits corresponding to the read group of bits;
• a unidirectional interface to receive, from the DRAM device, write check bits corresponding to the write group of bits, and to receive, from the DRAM device, read check bits corresponding to the read group of bits;
• and,
• a comparison circuit to determine, based on the write error check bits and the write check bits, whether a first error occurred, and to determine, based on the read error CRC check bits and the read check bits, whether a second error occurred.

A controller integrated circuit, comprising:

• a first plurality of transmitters to transmit, to a DRAM device via a command/address link, a first command for DRAM device to perform a first read operation, and to transmit a second command for DRAM device to perform a first write operation;
• a second plurality of transmitters to transmit, to the DRAM device via a bidirectional link, first write data corresponding to the first write operation;
• a first plurality of receiver circuits to receive, from the bidirectional link, first read data corresponding to the first read operation;
• an encoder circuit to generate first cyclic redundancy check (CRC) check information corresponding to the first read data, and to generate second CRC check information corresponding to the first write data;
• a receiver circuit to receive, first CRC information generated by the DRAM device and second CRC information generated by the DRAM device;
• and,
• a comparison circuit to determine, based on the first CRC check information and the first CRC information, whether a first error occurred, and to determine, based on the second CRC check information and the second CRC information, whether a second error occurred.