Instruction-optimizing processor with branch-count table in hardware

In a processing system having a microprocessor core, a hardware decoder arranged within the microprocessor core, and a translator, a method comprising:

• with the hardware decoder, decoding instructions for execution in the microprocessor core;
• in a logic structure arranged within the microprocessor core, tallying how many times the hardware decoder has decoded the instructions, wherein:
• the logic structure comprises a table comprising a plurality of registers, each respective register pre-loaded with an initial count value decremented each time a respective non-native code block has been uniquely decoded by the hardware decoder, the pre-loaded initial count value dependent on the respective non-native code block;
• and
• a first register in the plurality of registers is pre-loaded with a first initial count value and a second register in the plurality of registers is pre-loaded with a second initial count value, where the first initial count value and the second initial count value are different;
• translating and optimizing the respective non-native code block for execution in the microprocessor core when the respective register is decremented to zero;
• and
• storing the instructions as translated in a trace cache for execution by the processing system.

In a processing system having a microprocessor core, a hardware decoder arranged within the microprocessor core, and a translator, a method comprising:

• with the hardware decoder, decoding a non-native block of instruction code for execution in the microprocessor core, the non-native block of instruction code associated with a respective branch-target address;
• in a logic structure arranged within the microprocessor core, tallying a number of times that the hardware decoder decodes the non-native block of instruction code, the logic structure comprising a table comprising a plurality of registers addressable through one or more hashed forms of the branch-target address, wherein:
• each of the registers pre-loaded with an initial count value decremented each time the hardware decoder uniquely decodes a respective non-native block of instruction code, the pre-loaded initial count value dependent on the non-native code block of instruction code;
• and
• a first register in the plurality of registers is pre-loaded with a first initial count value and a second register in the plurality of registers is pre-loaded with a second initial count value, where the first initial count value and the second initial count value are different;
• raising an interrupt in the microprocessor when any of the plurality of registers underflows or holds a zero;
• in response to the interrupt being raised, translating and optimizing a respective non-native block of instruction code for execution via the translator;
• and storing the respective non-native block of instruction code, as translated, in a trace cache for subsequent execution by the processing system.