Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator

A system comprising:

• a register file;
• a binary translator to create a plurality of strands and a plurality of iteration windows, wherein each iteration window of the plurality of iteration windows is allocated a set of continuous registers of the register file;
• a plurality of buffers, wherein a buffer from the plurality of the buffers is to store strand documentation for a strand from the plurality of strands, wherein the strand documentation for the strand is to include an indication of a current register base for the strand, wherein the current register base for the strand indicates a set of registers that are allocated for the strand to use during execution;
• and
• a loop accelerator that includes a plurality of execution circuits, wherein the loop accelerator is communicatively coupled to the plurality of buffers and the register file, and wherein an execution circuit from the plurality of execution circuits is to execute a first instruction to update the current register base for the strand in the strand documentation for the strand based on a fixed step value and an iteration window size.