Compiler-assisted lookahead (CAL) memory system apparatus for microprocessors

An apparatus, for producing a compiler-assisted lookahead (CAL) memory system, a CAL processor system, a CAL memory management unit (MMU), and a CAL lookahead instructions (LI) and compatible instructions (CI) cache system, comprising:

• a CAL memory system;
• a CAL frontend processor;
• and
• a backend processor;
• wherein the apparatus for producing the CAL memory system for the CAL processor system is operable to:
• store lookahead instructions (LIs) and associated compatible instruction (CI) information blocks comprising CIs and related information fields comprising a CI access-termination field, a CI in-a-loop field, and any additional fields useful for the CAL processor system to the CAL memory system;
• wherein the LIs and the CI information blocks are transformed from the instructions of a program by a basic block compiler (BBC);
• wherein an LI is operable to:
• control flow of basic blocks in a program;
• determine the prefetch and/or fetch order of the basic blocks of the program;
• access the next LI for the LI prefetch and/or fetch;
• access the associated CI information block stored in the CAL memory system by providing a CI address;
• and
• access next LI without initiating any CI information block access;
• wherein the basic block is a straight-line code sequence:
• with only one branch in to an entry and only one branch out at an exit;
• without any branch to the entry and only branch out at the exit;
• and without any branch to the entry and out at the exit;
• wherein the CI information block comprising a CI access-termination bit, a CI in-a-loop bit, and a CI;
• wherein the CI information block is operable to:
• distinguish the last CI in the same basic block with the CI access-termination bit for terminating the CI prefetch and the CI fetch operations;
• identify the CI in a loop with the CI in-a-loop bit for reusing the CI information block already fetched during loop operation and for avoiding to fetch the same CI information block again from the CAL memory system;
• and
• produce compatible result of the instruction programmed before the BBC compilation with the CI;
• wherein the CIs are all other instructions in a basic block, excluding an instruction transformed to an LI of the basic block;
• fetch a single or plurality of LIs from the CAL memory system for lookahead branch prediction before fetching the associated CI information blocks from the CAL memory system to the CAL frontend processor in a sequential or parallel manner;
• predict branches of the LIs fetched to a branch predictor;
• reorder the LIs and the CI information blocks for the producing compatible results of decoding and execution;
• extract the CIs from the CI information blocks stored in a reorder buffer before decoding the CIs and the LIs;
• and
• fetch a single or plurality of LIs and the associated CI information blocks in a single or plurality of loops from the branch predictor and a reorder buffer or from a CI fetch queue, instead of fetching the LIs and the CI information blocks in the loop from the CAL memory system for enhancing performance and saving energy of the loop operation without fetching any of the LIs and the CI information blocks in the loop from the CAL memory system iteratively.