Paralleizing loops in the presence of possible memory aliases
AssigneeAnalog Devices Global
InventorsMichael G. Perkins, John L. Redford, Kaushal Sanghai
Life of this patent
Estimating the term…
Abstract
In one particular example, this disclosure provides an efficient mechanism to determine the degree of parallelization possible for a loop in the presence of possible memory aliases that cannot be resolved at compile-time. Hardware instructions are provided that test memory addresses at run-time and set a mode or register that enables a single instance of a loop to run the maximum number of SIMD (Single Instruction, Multiple Data) lanes to run in parallel that obey the semantics of the original scalar loop. Other hardware features that extend applicability or performance of such instructions are enumerated.
Claims20
A method to determine a degree of parallelization possible for a loop in a presence of possible memory aliases, comprising:
- providing hardware instructions that test memory addresses for pointer aliasing at run-time, at least in part, by determining a distance between the memory addresses, wherein the distance is measured in multiples of a data type;
- providing a scalar code that, when executed, performs a function;
- generating, from the scalar code, a vectorized code containing a same number of loops as the scalar code;
- and
- setting a mode or register that specifies a maximum number of Single Instruction, Multiple Data (SIMD) lanes on which to execute the vectorized code in parallel to perform the function of the scalar code, wherein the maximum number of SIMD lanes is the lesser of the distance and a number of SIMD lanes that are enabled.
An apparatus for determining a degree of parallelization possible for a loop in a presence of possible memory aliases, the apparatus comprising:
- at least one processing element for executing hardware instructions that test memory addresses for pointer aliasing at run-time, at least in part, by determining a distance between the memory addresses, wherein the distance is measured in multiples of a data type;
- a scalar code that, when executed, performs a function;
- a vectorized code containing a same number of loops as the scalar code;
- and
- a mode or register that is set to specify a maximum number of Single Instruction, Multiple Data (SIMD) lanes on which to execute the vectorized code in parallel to perform the function of the scalar code, wherein the maximum number of SIMD lanes is the lesser of the distance and a number of SIMD lanes that are enabled.
At least one machine readable non-transitory storage medium having instructions stored thereon for determining a degree of parallelization possible for a loop in a presence of possible memory aliases, wherein the instructions, when executed by at least one processor, causes the at least one processor to perform the following operations:
- execute hardware instructions that test memory addresses for pointer aliasing at run-time, at least in part, by determining a distance between the memory addresses, wherein the distance is measured in multiples of a data type;
- access a scalar code that, when executed, performs a function;
- generate, from the scalar code, a vectorized code containing a same number of loops as the scalar code;
- and
- set a mode or register that specifies a maximum number of Single Instruction, Multiple Data (SIMD) lanes on which to execute the vectorized code in parallel to perform the function of the scalar code, wherein the maximum number of SIMD lanes is the lesser of the distance and a number of SIMD lanes that are enabled.
Dependencies are inferred from the claim text.