Vector frequency expand instruction

A processor core comprising:

• a decode unit to decode an instruction into a decoded instruction, wherein the instruction includes a source operand and a destination operand, the source operand specifies a source vector that includes one or more pairs of a value and run length, and the run length represents a number of instances of the value in the run;
• and
• an execution unit to execute the decoded instruction to cause a set of one or more source data elements in the source vector to be expanded into a set of destination data elements comprising more elements than the set of one or more source data elements and including at least one run of identical values which were run length encoded in the source vector.

An article of manufacture comprising:

• a tangible machine-readable storage medium having stored thereon an instruction, wherein the instruction includes a source operand and a destination operand, the source operand specifies a source vector that includes one or more pairs of a value and run length, and the run length represents a number of instances of the value in the run;
• and
• wherein the instruction includes an opcode, which instructs a machine to execute the instruction to cause a set of one or more source data elements in the source vector to be expanded into a set of destination data elements comprising more elements than the set of one or more source data elements and including at least one run of identical values which were run length encoded in the source vector.