Operation of a multi-slice processor with reduced flush and restore latency

An apparatus comprising:

• a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, wherein the load/store slices are coupled to the execution slices via a results bus, wherein each execution slice comprises an issue queue, one or more general purpose registers, a history buffer, and a plurality of execution units including one or more floating point units and one or more vector scalar units;
• and
• a computer memory operatively coupled to the multi-slice processor, wherein the multi-slice processor is configured to carry out the steps of:
• for a target instruction targeting a logical register, determining whether an entry in a general purpose register representing the logical register is pending a flush;
• and
• when the entry in the general purpose register representing the logical register is pending a flush:
• cancelling the flush for the entry of the general purpose register;
• storing the target instruction in the entry of the general purpose register representing the logical register, and
• when an entry in a history buffer targeting the logical register is pending a restore, cancelling the restore for the entry of the history buffer.