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US 10,241,787 B2Granted
Control transfer override
AssigneeIntel Corporation
InventorPaul Caprioli
Life of this patent
Estimating the term…
Abstract
Embodiments of an invention for control transfer overrides are disclosed. In one embodiment, a processor includes an instruction unit to receive a control transfer instruction. The instruction unit includes a transfer override register to provide an alternative target for the control transfer instruction.
Claims15
A method comprising:
- programming, by software, a transfer override register in a processor to specify an alternative target address of a control transfer instruction having an original target address;
- enabling the transfer override register;
- issuing, to the processor, the control transfer instruction;
- loading, by an instruction fetch circuit in the processor in response to the control transfer instruction, an instruction register in the processor from the alternative target address instead of the original target address;
- calculating, in response to receiving the control transfer instruction when the programmable transfer override register is enabled, the original target address of the control transfer instruction;
- and
- storing, in response to receiving the control transfer instruction when the programmable transfer override register is enabled, the original target address of the control transfer instruction in an alternative instruction pointer register.
4 more elements
A processor comprising:
- an instruction unit to receive a control transfer instruction, the instruction unit including an instruction pointer register;
- an alternative instruction pointer register;
- an instruction register in which to store a current instruction to be executed by the processor;
- a programmable transfer override register to specify an alternative target address of a control transfer instruction;
- an instruction fetch circuit to load, in response to receiving the control transfer instruction, the instruction register from the alternative target address if the programmable transfer override register is enabled and from an original target address of the control transfer instruction if the programmable transfer override register is disabled;
- and
- hardware to, in response to receiving the control transfer instruction when the programmable transfer override register is enabled, calculate the original target address of the control transfer instruction and store the original target address of the control transfer instruction in the alternative instruction pointer register.
4 more elements
A system comprising:
- a memory in which to store first software and second software, wherein the first software includes a control transfer instruction having an original target address in the second software;
- and
- a processor including
- an instruction unit to receive a control transfer instruction, the instruction unit including
- an instruction pointer register;
- an alternative instruction pointer register;
- an instruction register in which to store a current instruction to be executed by the processor;
- a programmable transfer override register to specify an alternative target address of the control transfer instruction;
- an instruction fetch circuit to load, in response to receiving the control transfer instruction, the instruction register from the alternative target address if the programmable transfer override register is enabled and from the original target address of the control transfer instruction if the programmable transfer override register is disabled;
- and
- hardware to, in response to receiving the control transfer instruction when the programmable transfer override register is enabled, calculate the original target address of the control transfer instruction and store the original target address of the control transfer instruction in the alternative instruction pointer register.
8 more elements
Dependencies are inferred from the claim text.