Tiny detection in a floating-point unit
AssigneeInternational Business Machines Corporation
InventorsMichael K. Kroener, Silvia M. Mueller, Andreas Wagner
Life of this patent
Estimating the term…
Abstract
A floating-point unit for performing tiny detection in floating-point operations. The floating-point unit is configured to implement a fused-multiply-add operation on three wide operands. The floating-point unit comprise: a multiplier, a left shifter, a right shifter a select circuit comprising a 3-to-2 compressor, an adder connected to the dataflow from the select circuit, a first feedback path connecting a carry output) of the adder to the select circuit, and a second feedback path connecting an output of the adder to the left and right shifters for passing an intermediate wide result through the left and right shifters. The adder is configured to provide an unrounded result for tiny detection.
Claims13
A floating-point unit for performing tiny detection in floating-point operations, the floating-point unit comprising:
- a multiplier connected to a dataflow for multiplication two operands and configured to compute a carry-save product iteratively, wherein a sum term and a carry term are separated into a high part and a low part of the carry-save product;
- a left shifter connected to the dataflow for a high part and a low part of an addend operand, configured to deliver an aligned part of an addend;
- a right shifter connected to the dataflow for the high part and the low part of the addend operand, configured to deliver the aligned part of the addend;
- a select circuit connected to outputs of the left shifter and the right shifter, the select circuit comprising a 3-to-2 compressor to combine the sum term and the carry term with the addend;
- an adder connected to the dataflow from the select circuit;
- a first feedback path connecting a carry output of the adder to the select circuit, the first feedback path performing a wide addition operation of the carry-save product and the addend, for the high part and the low part of the carry-save product and the high part and the low part of the addend operand, in two subsequent additions, thus generating an intermediate wide result;
- a second feedback path connecting an output of the adder to the left shifter and the right shifter, the second feedback path passing the intermediate wide result through the left shifter and the right shifter for normalization and through the adder for rounding, thus generating a rounded result;
- and
- wherein the adder is configured to provide an unrounded result for the tiny detection in the floating-point operations.
Dependencies are inferred from the claim text.