Hybrid memory module with improved inter-memory data transmission path

A memory system comprising:

• one or more dynamic random access memory (DRAM) devices each comprising a first port coupled to a data bus comprising one or more data buffers;
• at least one non-volatile memory controller coupled to one or more flash memory devices;
• and
• at least one direct data transmission path coupling the at least one non-volatile memory controller and the one or more DRAM devices, the one or more DRAM devices each comprising a second port coupled to the at least one direct data transmission path to bypass the one or more data buffers,
• wherein the at least one non-volatile memory controller to use the at least one direct data transmission path to transmit data between the one or more DRAM devices and the one or more flash memory devices during a backup and restore operation, wherein the one or more DRAM devices are configured to enter a mode where a delay locked loop is turned off during the backup and restore operation when the direct data transmission path is in use, and
• wherein the one or more data buffers are disabled when transmitting data between the one or more DRAM devices and the one or more flash memory devices via the at least one direct data transmission path.

A memory system comprising:

• one or more dynamic random access memory (DRAM) devices each comprising a first port coupled to one or more data buffers;
• at least one non-volatile memory controller;
• and
• at least one direct data transmission path coupling the at least one non-volatile memory controller and the one or more DRAM devices, the one or more DRAM devices each comprising a second port coupled to the at least one direct data transmission path to bypass the one or more data buffers,
• wherein the at least one non-volatile memory controller to use the at least one direct data transmission path to transmit data to the one or more DRAM devices or receive data from the one or more DRAM devices during a backup and restore operation, wherein the one or more DRAM devices are configured to enter a mode where a delay locked loop is turned off during the backup and restore operation when the direct data transmission path is in use, and
• wherein the one or more data buffers are disabled when transmitting data to the one or more DRAM devices or receiving data from the one or more DRAM devices via the at least one direct data transmission path.