Combined transparent/non-transparent cache

A system comprising:

• at least one processor;
• a main memory system, wherein locations in the main memory system are mapped to a first subset of addresses in a memory address space;
• and
• a memory coupled between the main memory system and the processor, wherein:
• the memory is delineated into a first portion and a second portion;
• the first portion is a cache memory, and locations in the cache memory are temporarily mapped to addresses in the first subset of addresses in the memory address space via hardware controlling the cache memory;
• the second portion is mapped to a second subset of addresses in the memory address space;
• and
• the main memory system is configured to store a plurality of instructions executable by the processor to directly control storage of data in the second portion using the second subset of addresses.

An apparatus comprising:

• a control circuit;
• and
• a memory coupled to the control circuit, wherein:
• the control circuit is programmable with a delineation of the memory into a first portion and a second portion;
• the control circuit is configured to operate the first portion as a cache memory having corresponding locations in a main memory system;
• the second portion is addressed directly by memory requests, and locations in the second portion do not have corresponding locations in the main memory system.