Solid state memory system with power management mechanism and method of operation thereof

A solid state memory system comprising:

• an interface circuit;
• a device processor, coupled to the interface circuit, configured to receive a dynamic power limit command through the interface circuit and update a metadata log based on the dynamic power limit command and wherein the device processor is further configured to suspend background tasks, utilize only low power pages, update the metadata log with adjusted threshold for reduced voltage writes, and provide continued operation based on the dynamic power limit command;
• a non-volatile memory array coupled to the interface circuit;
• and
• a power manager unit, coupled to the device processor, configured by the device processor, wherein the device processor loads registers in the power manager unit to alter an operating configuration of the non-volatile memory array to meet the requirement of the dynamic power limit command received by the device processor, the power manager unit configured to adjust voltages for read, write, erase, and monitoring a voltage feedback in order to verify the dynamic power limit command is not exceeded.