Method for operating semiconductor device and semiconductor system
AssigneeSamsung Electronics Co., Ltd.
InventorSeung-Soo Yang
Life of this patent
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Abstract
A method for operating a semiconductor device includes receiving a memory request for a memory; calculating a memory bandwidth such that the memory bandwidth is at least large enough to support allocation of the memory in accordance with the memory request; creating a memory path for accessing the memory using a memory hierarchical structure wherein a memory region that corresponds to the memory path is a memory region that is allocated to support the memory bandwidth; and performing memory interleaving with respect to the memory region that corresponds to the memory path.
Claims18
A method for operating a volatile semiconductor memory device comprising:
- receiving a memory request for memory of the volatile semiconductor memory device;
- calculating a memory bandwidth such that the memory bandwidth is at least large enough to support allocation of the memory in accordance with the memory request;
- creating a memory path for accessing the memory using a memory hierarchical structure, wherein the creating the memory path comprises selecting one of a plurality of channels of the memory and selecting at least one of a plurality of ranks of the selected one of the plurality of channels, wherein a memory region of the memory that corresponds to the memory path is a memory region that is allocated to support the memory bandwidth and the memory region comprises the selected one of the plurality of channels and the selected at least one of the plurality of ranks;
- and
- performing memory interleaving with respect to the memory region that corresponds to the memory path,
- wherein the performing the memory interleaving includes,
- operating the memory region of the memory that corresponds to the memory path in a normal power mode;
- and
- operating a memory region of the memory that does not correspond to the memory path in a low power mode, the low power mode being a self-refresh mode that uses less power than the normal power mode.
A method for operating a volatile semiconductor memory device comprising:
- receiving a memory request for memory of the volatile semiconductor memory device;
- calculating a memory bandwidth such that the memory bandwidth is at least large enough to support allocation of the memory in accordance with the memory request;
- selecting one of a plurality of ranks of the memory and at least one of a plurality of channels that support the memory bandwidth and the plurality of channels including the plurality of ranks;
- and
- performing memory interleaving with respect to the selected the one of the plurality of ranks and the at least one of the plurality of channels,
- operating a memory region that corresponds to non-selected ranks and channels among the plurality of ranks and the plurality of channels of the memory in a low power mode, the low power mode being a self-refresh mode that uses less power than a power mode in which a memory region that corresponds to the selected ranks and channels among the plurality of ranks and the plurality of channels is operated.
A method of operating a semiconductor memory device including a plurality of memory groups, the method comprising:
- receiving a memory request for accessing memory of the semiconductor memory device;
- determining, based on the memory request, a first data rate;
- allocating a first portion of the plurality of memory groups such that,
- the first portion includes one or more memory groups from among the plurality of memory groups and excludes one or more memory groups from among the plurality of memory groups, and
- a number of groups in the first portion of the plurality of memory groups is based on the first data rate;
- and
- mapping physical addresses corresponding to the first portion of the plurality of memory groups to virtual address space;
- and
- executing the memory request by performing memory interleaving on the first portion of the plurality of memory groups with respect to the physical addresses mapped to the virtual address space and not on a second portion of the plurality of memory groups, the second portion being the one or more memory groups excluded from the first portion,
- the executing including operating the first portion of the plurality of memory groups in a first power mode and operating the second portion of the plurality of memory groups in a second power mode, the second power mode being a self-refresh mode that uses less power than the first power mode.
Dependencies are inferred from the claim text.