US 10,241,561 B2 · Adaptive power down of intra-chip interconnect

Abstract

The hash function used by the processors on a multi-processor chip to distribute accesses to the various last-level caches via the links is changed according to which last-level caches (and/or links) that are active (e.g., ‘on’) and which are in a lower power consumption mode (e.g., ‘off’.) A first hash function is used to distribute accesses to all of the last-level caches and all of the links when all of the last-level caches are ‘on.’ A second hash function is used to distribute accesses to the appropriate subset of the last-level caches and corresponding subset of links when some of the last-level caches are ‘off.’ Data can be sent to only the active last-level caches via active links. By shutting off links connected to caches and components that are in a lower power consumption mode, the power consumption of the chip is reduced.

Claims20

Dependent claims

An integrated circuit, comprising:

a plurality of last-level caches that can be placed in at least a first high cache-power consumption mode and a first low cache-power consumption mode, the plurality of last-level caches including a first last-level cache and a second last-level cache;
a plurality of processor cores to access data in the plurality of last-level caches;
and,
an interconnect network, comprised of a plurality of point-to-point links that can be placed in at least a first high link-power consumption mode and a first low link-power consumption mode, to receive access addresses from the plurality of processor cores and to couple, via respective subsets of the plurality of point-to-point links, each of the plurality of processor cores to a respective one of the plurality of last-level caches, a first subset of the plurality of point-to-point links to be placed in the first low link-power consumption mode based at least in part on the first last-level cache being in the first low cache-power consumption mode.

1 more element

Dependencies are inferred from the claim text.

Adaptive power down of intra-chip interconnect

Life of this patent

Adaptive power down of intra-chip interconnect

Life of this patent

Abstract

Claims20