System and method for dynamically switching high-speed clock of a host device
AssigneeWipro Limited
InventorVijay Kumar Kodavalla
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Abstract
This disclosure relates generally to a host-peripheral interface, and more particularly to an apparatus and method for dynamically switching a high-speed clock of a host device. In one embodiment, a method is provided for dynamically switching a high-speed clock of a host device. The method comprises determining a status of the host device and a peripheral device coupled to the host device with respect to a transmission and a reception of high-speed data respectively, and switching the high-speed clock between the host device and the peripheral device based on the status.
Claims18
A method for dynamically switching a source synchronous high-speed clock of a host device in a mobile industry processor interface (MIPI) system, the method comprising:
- determining, by at least one of configurable hardware logic or a processor, a status of the host device and a peripheral device coupled to the host device with respect to a transmission and a reception of high-speed data respectively during high-speed data transfer in burst data and non-continuous clock mode;
- switching-ON or switching-OFF, by the at least one of the configurable hardware logic or the processor, the source synchronous high-speed clock between the host device and the peripheral device based on the status of the host device and the peripheral device;
- detecting, by the at least one of the configurable hardware logic or the processor, an end of the high-speed data transfer, wherein the end of the high-speed data transfer is detected based on an end of line or end of frame of the high-speed data;
- and
- switching, by the at least one of the configurable hardware logic or the processor, a plurality of data lanes to a low-power mode upon detecting the end of the high-speed data transfer, the source synchronous high-speed clock being switched-OFF based on the low-power mode.
A switching apparatus for dynamically switching a source synchronous high-speed clock of a host device in a mobile industry processor interface (MIPI) system, comprising:
- at least one of configurable hardware logic configured to be capable of implementing programmed instructions or a processor coupled to a memory and configured to execute programmed instructions stored in the memory to;
- determine a status of the host device and a peripheral device coupled to the host device with respect to a transmission and a reception of high-speed data respectively during high-speed data transfer in burst data and non-continuous clock mode;
- switch-ON or switch-OFF the source synchronous high-speed clock between the host device and the peripheral device based on the status of the host device and the peripheral device;
- detect an end of the high-speed data transfer, wherein the end of the high-speed data transfer is detected based on an end of line or end of frame of the high-speed data;
- and
- switch a plurality of data lanes to a low-power mode upon detecting the end of the high-speed data transfer, the source synchronous high-speed clock being switched-OFF based on the low-power mode.
A non-transitory computer readable medium having stored thereon instructions for dynamically switching a source synchronous high-speed clock of a host device in a mobile industry processor interface (MIPI) system, the instructions comprising machine executable code which when executed by at least one processor, causes the at least one processor to perform steps comprising:
- determining a status of the host device and a peripheral device coupled to the host device with respect to a transmission and a reception of high-speed data respectively during high-speed data transfer in burst data and non-continuous clock mode;
- switching-ON or switching-OFF the source synchronous high-speed clock between the host device and the peripheral device based on the status of the host device and the peripheral device;
- detecting an end of the high-speed data transfer, wherein the end of the high-speed data transfer is detected based on an end of line or end of frame of the high-speed data;
- and
- switching a plurality of data lanes to a low-power mode upon detecting the end of the high-speed data transfer, the source synchronous high-speed clock being switched-OFF based on the low-power mode.
Dependencies are inferred from the claim text.