Reducing power consumption in a processor

A processor comprising:

• a fetch prediction unit including:
• a next fetch prediction unit including a first plurality of prediction entries for respective next instruction fetch groups, wherein the next fetch prediction unit is configured to assert a first enable signal for a memory of a branch prediction unit in response to a determination that a particular one of the first plurality of prediction entries indicates that a subsequent next instruction fetch group includes a conditional branch instruction;
• and
• a sequential fetch prediction unit including a second plurality of prediction entries, wherein the sequential fetch prediction unit is accessed by the fetch prediction unit after receiving an indication that a subsequent next instruction fetch group includes a conditional branch instruction, wherein each of the second plurality of prediction entries corresponds to a respective entry of the first plurality of prediction entries, and wherein, the sequential fetch prediction unit is configured to, for those entries in the first plurality that indicate a next instruction fetch group having a conditional branch instruction, assert a second enable signal for the memory of the branch prediction unit in response to a determination that a particular entry in the second plurality indicates that a sequential instruction fetch group following the conditional branch instruction includes a further conditional branch instruction.