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US 10,241,556 B2Granted
Autonomously controlling a buffer of a processor
AssigneeIntel Corporation
InventorsVinu K. Elias, Sundar Ramani, Arvind S. Tomar, Jianjun Liu
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Abstract
In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.
Claims19
An apparatus comprising:
- an input/output (I/O) buffer coupled to a logic circuit of the apparatus;
- a pad to couple an external device to the I/O buffer of the apparatus;
- and
- a control logic circuit coupled to the I/O buffer to:
- sample a state on the pad subsequent to a first entry into low power state of the apparatus;
- determine a first control value for the I/O buffer based on the sampled state and the low power state of the apparatus;
- store the first control value in a configuration storage associated with the I/O buffer;
- in response to a second entry into the low power state of the apparatus, control the I/O buffer to maintain the sampled state at the pad using the stored first control value.
5 more elements
A system comprising:
- a processor formed in an integrated circuit (IC), the processor including:
- at least one core;
- an input/output (I/O) controller having a power management logic circuit;
- and
- at least one input/output (I/O) buffer coupled to the I/O controller to communicate signal information with one or more devices coupled to the processor,
- wherein the power management logic circuit is to:
- receive an indication of a first entry into a low power state of at least a portion of the processor,
- responsive the first entry, sample a state on a pad of the IC, the pad coupled between the at least one I/O buffer and an interconnect,
- determine a first control value for the at least one I/O buffer based on the sampled state and the low power state,
- store the first control value in a configuration storage associated with the I/O buffer,
- in response to a second entry into the low power state, control the I/O buffer to maintain the sampled state at the pad using the stored first control value;
- and
- a dynamic random access memory (DRAM) coupled to the processor.
10 more elements
A method comprising:
- responsive to a first entry into a low power state, sampling a state on a pad of an integrated circuit (IC) coupled to an interconnect, the pad coupled to a buffer of the IC, the buffer including a transmitter and a receiver;
- selecting a first control value for at least one controllable element of the buffer based on the sampled state and the low power state;
- storing the selected first control value in a storage associated with the buffer;
- and
- in response to a second entry into the low power state, controlling the buffer to maintain the sampled state at the pad using the stored first control value.
2 more elements
Dependencies are inferred from the claim text.