Resynchronization of a clock associated with each data bit in a double data rate memory system

An apparatus comprising:

• an input interface comprising a plurality of input stages each configured to (i) receive (a) a data signal and (b) a clock signal through a first clock tree and (ii) present an intermediate signal;
• an output interface comprising a plurality of output stages each configured to (i) receive said intermediate signal from one of said input stages, (ii) receive an adjusted clock signal and (iii) present an output signal;
• and
• an adjustment circuit comprising a plurality of adjustment components each configured to (i) receive said clock signal through a second clock tree, (ii) receive a reference clock signal, and (iii) generate said adjusted clock signals presented to each of said output stages, wherein (a) said adjustment circuit is located near said output interface, and (b) each of said adjustment components is configured to resynchronize said clock signal for each respective bit transmitted from said input interface to said output interface to reduce a bit to bit delay caused by said clock tree.