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US 10,241,470 B2Granted
No miss cache structure for real-time image transformations with data compression
AssigneeMicrosoft Technology Licensing, LLC
InventorsTolga Ozguner, Gene Leung, Jeffrey Powers Bradford, Adam James Muff, Miguel Comparan, Ryan Scott Haraden, Christopher Jon Johnson
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Abstract
Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.
Claims23
A head-mounted, augmented, mixed or virtual reality display device (HMD) comprising:
- a display;
- a graphics processing unit (GPU) that generates images that can include text, holographic objects and other visual elements that can be displayed on the display;
- system memory that stores GPU images as compressed image data;
- a holographic processing unit (HPU), with an on-chip cache, the HPU configured to perform late stage adjustments to correct GPU images for movement of the HMD that may occur during the image rendering process, the cache for constructing an output image based on the GPU generated image and the late stage adjustments, the cache being divided into a first cache and a second cache, and the HPU generating a late stage adjustment matrix that maps each pixel of the late stage adjusted output image to the corresponding pixel of the GPU image;
- one or more processors;
- and
- one or more physical computer-readable storage media having stored thereon instructions that are executable by the one or more processors to configure the HPU to perform at least the following acts:
- retrieving and decompressing one or more tiles of compressed GPU image data from system memory and placing the decompressed GPU image data in the first cache, the one or more tiles being selected in the order needed to construct the output image;
- retrieving one or more rows of decompressed image data from the first cache, the one or more rows being selected in the order needed to construct the output image;
- writing the one or more rows of decompressed GPU image data into the second cache in the order needed to construct the output image based on the late stage adjustment matrix;
- constructing the output image by walking the one or more rows of the GPU image in the second cache according to the adjustment matrix and outputting the output image;
- and
- wherein the size and power consumption properties of the cache are kept as small as possible and yet the cache is sized such that each line of input image data is fetched only once during the process of performing the late stage adjustments and constructing the output image so as to reduce input bandwidth requirements.
10 more elements
A head-mounted, augmented, mixed or virtual reality display device (HMD) comprising:
- a display;
- a graphics processing unit (GPU) that generates images that can include text, holographic objects and other visual elements that can be displayed on the display;
- system memory that stores GPU images as compressed image data;
- a holographic processing unit (HPU), with an on-chip cache, the HPU configured to perform late stage adjustments to correct GPU images for movement of the HMD that may occur during the image rendering process, the cache for constructing an output image based on the GPU generated image and the late stage adjustments, the cache being divided into a first cache, a second cache and a third cache, and the HPU generating a late stage adjustment matrix that maps each pixel of the late stage adjusted output image to the corresponding pixel of the GPU image;
- one or more processors;
- and
- one or more physical computer-readable storage media having stored thereon instructions that are executable by the one or more processors to configure the HPU to perform at least the following acts:
- retrieving one or more tiles of compressed GPU image data from system memory and placing the compressed GPU image data in the first cache, the one or more tiles of compressed GPU image data being selected in the order needed to construct the output image;
- retrieving and decompressing one or more tiles of compressed GPU image data from the first cache and placing the decompressed GPU image data in the second cache, the one or more tiles being selected in the order needed to construct the output image;
- retrieving one or more rows of decompressed GPU image data from the second cache and writing the one or more rows of decompressed GPU image data into the third cache in the order needed to construct the output image based on the late stage adjustment matrix;
- constructing the output image by walking the one or more rows of the decompressed GPU image data in the third cache according to the adjustment matrix and outputting the output image;
- and
- wherein the size and power consumption properties of the cache are kept as small as possible and yet the cache is sized such that each line of input image data is fetched only once during the process of performing the late stage adjustments and constructing the output image so as to reduce input bandwidth requirements.
10 more elements
Dependencies are inferred from the claim text.