Radio-frequency loss reduction in photonic circuits
AssigneeAurrion, Inc.
InventorsJohn Parker, Gregory Alan Fish, Brian R. Koch
Life of this patent
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Abstract
In photonic integrated circuits implemented in silicon-on-insulator substrates, non-conductive channels formed, in accordance with various embodiments, in the silicon device layer and/or the silicon handle of the substrate in regions underneath radio-frequency transmission lines of photonic devices can provide breaks in parasitic conductive layers of the substrate, thereby reducing radio-frequency substrate losses.
Claims19
A method of fabricating an integrated photonic circuit (PIC) from a silicon-on-insulator substrate comprising a silicon handle, a buried oxide layer disposed on top of the silicon handle, and a silicon device layer disposed on top of the buried oxide layer, the method comprising:
- patterning and partially etching the silicon device layer to form at least portions of waveguides in the silicon device layer;
- following the partial etching, patterning and etching the silicon device layer down to the buried oxide layer to form one or more conductivity-breaking channels in the silicon device layer between the waveguides;
- depositing a dielectric material on top of the etched silicon device layer to form a cladding layer;
- embedding, in the cladding layer, III-V waveguides above the waveguides in the silicon device layer;
- and
- depositing, patterning, and etching electrode metals on top of the cladding layer to create electrodes of a transmission line, wherein the created electrodes are placed such that the conductivity-breaking channels are located in a region underneath the transmission line, overlapping with a gap defined between the electrodes and not extending beyond outer edges of the electrodes.
A method of fabricating an integrated photonic circuit (PIC) from a silicon-on-insulator substrate comprising a silicon handle, a buried oxide layer disposed on top of the silicon handle, and a silicon device layer disposed on top of the buried oxide layer, the method comprising:
- depositing, patterning, and etching dielectric and III-V layers to create a dielectric cladding on top of the silicon device layer and, embedded within the dielectric layer, one or more III-V optical waveguides;
- creating, on top of the cladding, a transmission line comprising two electrodes defining a gap therebetween, the gap laterally overlapping with at least one of the one or more III-V optical waveguides;
- and
- patterning and etching the silicon handle to form therein a nonconductive channel overlapping with the gap defined between the two electrodes and not extending beyond outer edges of the electrodes.
A method of fabricating an integrated photonic circuit (PIC) from a silicon-on-insulator substrate comprising a silicon handle, a buried oxide layer disposed on top of the silicon handle, and a silicon device layer disposed on top of the buried oxide layer, the method comprising:
- patterning and etching at least one of the silicon device layer or one or more dielectric or III-V layers deposited above the silicon device layer to create optical components of a first photonic device and of one or more second photonic devices in at least one of the silicon device layer or the one or more dielectric or III-V layers;
- creating a transmission line above an optical component of the first photonic device, the transmission line comprising two or more electrodes defining one or more gaps therebetween;
- and
- patterning and etching at least one of the silicon device layer or the silicon handle to form therein one or more nonconductive channels each extending throughout the silicon device layer or silicon handle and overlapping with one of the one or more gaps, the one or more nonconductive channels being confined to a region encompassing only the first photonic device.
Dependencies are inferred from the claim text.