Massively parallel wafer-level reliability system and process for massively parallel wafer-level reliability testing
AssigneeThe United States of America as represented by the Secretary of Commerce
InventorKin P. Cheung
Life of this patent
Estimating the term…
Abstract
A massively parallel wafer-level reliability system to test a reliability of wafers includes: a test platform; stations disposed on the test platform, wherein an individual test station receives a wafer and includes: a chuck disposed on the test platform; a probe including contactors that electrically contact the wafer; and a temperature controller to control a temperature of the wafer; a control platform disposed among the test stations; and a system controller to independently control the test stations and that is in electrical communication with the temperature controller, wherein the reliability of the wafers is tested in parallel by the test stations.
Claims20
A massively parallel wafer-level reliability system to test a reliability of a plurality of wafers, the system comprising:
- a test platform;
- a plurality of test stations disposed on the test platform, wherein an individual test station receives a wafer of the plurality of wafers and comprises:
- a chuck disposed on the test platform to receive the wafer;
- a probe comprising a plurality of contactors, the contactors to electrically contact the wafer disposed on the chuck;
- and
- a temperature controller disposed on the chuck to control a temperature of the wafer disposed on the chuck;
- a control platform disposed among the plurality of test stations, the test platform and the control platform having relative motion such that the test stations are selectively positioned with respect to a location of a fiduciary disposed on the control platform;
- and
- a system controller disposed on the control platform to independently control the test stations and in electrical communication with the temperature controller,
- wherein the reliability of the wafers is tested in parallel by the test stations.
A process for massively parallel wafer-level reliability testing, the process comprising:
- providing a massively parallel wafer-level reliability system that comprises:
- a test platform;
- a plurality of test stations disposed on the test platform, wherein an individual test station comprises:
- a chuck disposed on the test platform;
- a probe comprising a plurality of contactors, the contactors to electrically contact the wafer disposed on the chuck;
- and
- a temperature controller disposed on the chuck to control a temperature of the wafer disposed on the chuck;
- a control platform disposed among the plurality of test stations, the test platform and the control platform having relative motion such that the test stations are selectively positioned with respect to a location of a fiduciary disposed on the control platform, and
- a system controller disposed on the control platform and in electrical communication with the temperature controller,
- disposing a plurality of wafers on the massively parallel wafer-level reliability system such that individual test stations receive a wafer disposed on the chuck;
- contacting the wafer disposed on the chuck with the contactors of the probe;
- and
- testing, in parallel, a reliability of the wafers to perform massively parallel wafer-level reliability testing.
Dependencies are inferred from the claim text.