Virtual access of input/output (I/O) for test via an on-chip star network

A method for testing an integrated circuit that includes an on-chip star network, the method comprising:

• causing each test multiplexer included in a plurality of test multiplexers located on the integrated circuit to couple a different input/output (I/O) pad of the integrated circuit to the on-chip star network;
• causing a digital-to-analog converter (DAC) located on the integrated circuit to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network;
• and
• causing a wide-range comparator located on the integrated circuit to compare a voltage present on a selected I/O pad with a second reference voltage, wherein a first test multiplexer included in the plurality of test multiplexers couples to a first I/O pad included in the plurality of I/O pads and further couples the wide-range comparator to the on-chip star network.

A non-transitory computer-readable storage medium including instructions that, when executed by a processor, cause the processor to test an integrated circuit that includes an on-chip star network, by performing the steps of:

• causing each test multiplexer included in a plurality of test multiplexers located on the integrated circuit to couple a different input/output (I/O) pad of the integrated circuit to the on-chip star network;
• causing a digital-to-analog converter (DAC) located on the integrated circuit to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network;
• and
• causing a wide-range comparator located on the integrated circuit to compare a voltage present on a selected I/O pad with a second reference voltage, wherein a first test multiplexer included in the plurality of test multiplexers couples to a first I/O pad included in the plurality of I/O pads and further couples the wide-range comparator to the on-chip star network.