# US 10,236,872 B1 · AC coupling modules for bias ladders

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- Number: US 10,236,872 B1
- Document ID: US10236872B1
- Status: Granted
- Kind: B1
- Application number: 15/939,144
- Filed: 2018-03-28
- Granted: 2019-03-19
- Earliest claimed: 2018-03-28
- Assignees: pSemi Corporation
- Applicants: pSemi Corporation
- Inventors: Simon Edward Willard; Tero Tapio Ranta
- Web page: https://patentgrep.com/patent/US10236872B1

## CPC

- H03K 17/102: {in field-effect transistor switches}
- H03K 17/0412: by measures taken in the control circuit
- H03K 17/063: {in field-effect transistor switches}
- H03K 17/162: {without feedback from the output circuit to the control circuit}
- H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor}
- H03K 17/6872: {using complementary field-effect transistors}
- H03K 17/6874: {in a symmetrical configuration}
- H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00)
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/813: {Combinations of field-effect devices and capacitor only}
- H10D 84/817: {Combinations of field-effect devices and resistors only}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10W 90/00: Package configurations
- H03K 2017/066: {Maximizing the OFF-resistance instead of minimizing the ON-resistance}
- H03K 2217/0009: AC switches, i.e. delivering AC power to a load
- H03K 2217/0054: Gating switches, e.g. pass gates
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

## Claims

### Claim 1

A FET switch stack, including:
(a) a plurality of series-coupled FETs, including a first end FET having a first signal terminal and a second end FET having a second signal terminal;
(b) a gate bias resistor ladder coupled to the gates of the series-coupled FETs and configured to be coupled to a gate control voltage that controls the ON or OFF switch state of each series-coupled FET; and
(c) an AC coupling gate module coupled to at least one end of the gate bias resistor ladder and configured to be coupled to a radio frequency voltage source;
wherein in response to the OFF switch state of each series-coupled FET, a signal applied to the first or second signal terminal is blocked from conduction through the plurality of series-coupled FETs, and wherein in response to the ON switch state of each series-coupled FET, a signal applied to the first or second signal terminal is conducted through the plurality of series-coupled FETs.

### Claim 2

A FET switch stack, including:
(a) a plurality of series-coupled FETs;
(b) a gate bias resistor ladder coupled to the gates of the series-coupled FETs;
(c) an AC coupling gate module coupled to at least one end of the gate bias resistor ladder and configured to be coupled to a corresponding radio frequency voltage source;
(d) a body charge control resistor ladder coupled to the bodies of the series-coupled FETs; and
(e) an AC coupling body module coupled to at least one end of the body charge control resistor ladder and configured to be coupled to the corresponding radio frequency voltage source.

### Claim 3 (depends on 1, 2)

The invention of claims 1 or 2, wherein the plurality of series-coupled FETs includes one or more series-coupled positive-logic FET, series-coupled on at least one end to an end-cap FET that turns OFF when the VGS of such end-cap FET is essentially zero volts.

### Claim 4 (depends on 3)

The invention of claim 3, further including a second end-cap FET that turns OFF when the VGS of such end-cap FET is essentially zero volts, series-coupled to a second end of the one or more series-coupled positive-logic FETs.

### Claim 5 (depends on 3)

The invention of claim 3, further including a drain-source resistor ladder including a plurality of series-coupled resistors configured to be coupled to a drain-source bias voltage, wherein each resistor is coupled to the respective drains and sources of corresponding adjacent positive-logic FETs.

### Claim 6 (depends on 1, 2)

The invention of claims 1 or 2, wherein the gate bias resistor ladder includes a plurality of series-connected resistors.

### Claim 7 (depends on 2)

The invention of claim 2, wherein the body charge control resistor ladder includes a plurality of series-connected resistors.

### Claim 8 (depends on 1, 2)

The invention of claims 1 or 2, wherein the AC coupling gate module includes one of a capacitor or a capacitor series coupled to a resistor.

### Claim 9 (depends on 2)

The invention of claim 2, wherein the AC coupling body module includes one of a capacitor or a capacitor series coupled to a resistor.

### Claim 10 (depends on 1, 2)

The invention of claims 1 or 2, wherein the gate bias resistor ladder is configured to be coupled to a bias voltage at a node at a first end of the gate bias resistor ladder.

### Claim 11 (depends on 1, 2)

The invention of claims 1 or 2, wherein the gate bias resistor ladder is configured to be coupled to a bias voltage at a node between a first end and a second end of the gate bias resistor ladder.

### Claim 12 (depends on 1, 2)

The invention of claims 1 or 2, wherein at least one FET is an ACS FET.